LTC5587IDD Ver la hoja de datos (PDF) - Linear Technology
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LTC5587IDD Datasheet PDF : 20 Pages
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LTC5587
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =
fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.
SYMBOL
PARAMETER
CIN
SCK, CONV Input Capacitance
VOH
SDO Logic High Output
VOL
SDO Logic Low Output
IOZ
Hi-Z Output Leakage
COZ
Hi-Z Output Capacitance
ISOURCE
SDO Source Current
ISINK
SDO Sink Current
Detector Enable (EN) Low = Off, High = On
PARAMETER
EN Input High Voltage (On)
EN Input Low Voltage (Off)
Enable Pin Input Current
Turn ON Time; CW RF Input
Turn OFF Time; CW RF Input
Power Supply
OVDD Supply Voltage
VDD Supply Voltage
VREF Reference Voltage
VCC Supply Voltage
Total Supply Current
Shutdown Current
CONDITIONS
ISOURCE = 200μA
ISINK = 200μA
CONV = VDD
CONV = VDD
SDO Connected to GND = 0V
SDO Connected to VDD
CONDITIONS
EN = 3.3V
VOUT within 10% of Final Value; PIN = 0dBm
VOUT < 0.18V; PIN = 0dBm
Should Be Equal to VDD
No RF Input Signal, ADC Operational at 500ksps
No RF Input Signal, ADC Sleep-Mode
EN = 0.3V, CONV = 3.3V, ADC Sleep-Mode
MIN
TYP
MAX
2
l VDD – 0.2
l
0.2
l
±3
4
–10
10
MIN TYP
MAX
l
2
l
0.3
25
1
8
l
1
l 2.7
l 1.4
l 2.7
l
l
3.3
VDD
3.3
3.6
VDD + 0.05
3.3
3.6
3
4
1.4
2.5
0.2
10
UNITS
pF
V
V
μA
pF
mA
mA
UNITS
V
V
μA
μs
μs
V
V
V
V
mA
mA
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. The maximum RF input power rating is guaranteed
by design and engineering characterization, but not production tested.
Note 2: The LTC5587 is guaranteed to be functional over the operating
temperature range from –40°C to 85°C.
Note 3: The linearity error is calculated by the difference between the
incremental slope of the output and the average output slope from –20dBm
to 0dBm. The dynamic range is defined as the range over which the
linearity error is within ±1dB.
Note 4: An external capacitor at the CSQ pin should be used for input
frequencies below 250MHz. Without this capacitor, lower frequency
operation results in excessive RF ripple in the output voltage.
Note 5: Logarithmic intercept is an extrapolated input power level from
the best fitted log-linear straight line, where the converted output code is
0LSB.
Note 6: PSRR determined as the dB value of the change in converted
output voltage over the change in VCC supply voltage at a given CW input
power level.
Note 7: Guaranteed by design not subject to test.
Note 8: Guaranteed by characterization. All input signals are specified with
tR = tF = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: The time required for the output to cross the VIH or VIL voltage.
Note 11: When pins VOUT and VREF are taken below GND or above VDD,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below GND or above VDD without latchup.
Note 12: The VDD supply voltage can be the same as VCC and the pins can
share a common bypass capacitor of 2.2μF.
5587f
5
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