LTC4357 Ver la hoja de datos (PDF) - Linear Technology
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LTC4357 Datasheet PDF : 12 Pages
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LTC4357
APPLICATIONS INFORMATION
VDD Hold-Up Circuit
In the event of an input short, parasitic inductance between
the input supply of the LTC4357 and the load bypass
capacitor may cause VDD to glitch below its minimum
operating voltage. This causes the turn-off time (tOFF) to
increase.
To preserve the fast turn-off time, local output bypassing
of 39μF is sufficient at voltages less than 30V. At higher
voltages, 100μF is adequate. As an alternative to local
bypassing, a 100Ω, 0.1μF RC hold-up circuit on the VDD
pin can be used, shown in Figure 2. In applications with
unusually large inductance or load current greater than
10A, use 100Ω and 1μF.
Design Example
The following design example demonstrates the calcula-
tions involved for selecting components in a 12V system
with 10A maximum load current (see Figure 3).
First, calculate the RDS(ON) of the MOSFET to achieve
the desired forward drop at full load. Assuming VDROP
= 0.1V,
RDS(ON)
VDROP
I LOAD
=
0.1V
10A
RDS(ON) 10m
The Si4874DY offers a good solution, in an S8 package
with RDS(ON) = 10mΩ(max) and BVDSS of 30V.
The maximum power dissipation in the MOSFET is:
P = ILOAD2 • RDS(ON) = (10A)2 • 10mΩ = 1W
With less than 39μF of local bypass, the recommended RC
values of 100Ω and 0.1μF were used in Figure 3.
Since BVDSS + VIN is much less than 100V, output clamp-
ing is unnecessary.
VIN
Si4874DY
12V
IN
GATE
OUT
LTC4357
VDD
GND
CBYPASS
39μF
VIN1
12V
IN
Si4874DY
GATE
OUT
LTC4357
VDD
GND
100Ω
VOUT
TO LOAD
0.1μF
VIN
Si4874DY
12V
R1
IN
GATE
OUT
100Ω
LTC4357
VDD
GND
C1
0.1μF
4357 F02
Figure 2. Two Methods of Protecting Against Collapse
of VDD From Input Short and Stray Inductance
VIN2
12V
IN
Si4874DY
GATE
OUT
LTC4357
VDD
GND
100Ω
0.1μF
4357 F03
Figure 3. 12V, 10A Diode-OR
4357fb
8
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