LTC485CJ8 Ver la hoja de datos (PDF) - Linear Technology

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LTC485CJ8

Low Power RS485 Interface Transceiver

Linear Technology 

LTC485

UU W U

APPLICATIO S I FOR ATIO

The LTC485 output stage will maintain a high impedance

state until the breakdown of the N-channel or P-channel is

reached when going positive or negative respectively. The

output will be clamped to either VCC or ground by a Zener

voltage plus a Schottky diode drop, but this voltage is way

beyond the RS485 operating range. This clamp protects

the MOS gates from ESD voltages well over 2000V.

Because the ESD injected current in the N-well or substrate

consists of majority carriers, latchup is prevented by

careful layout techniques.

Propagation Delay

Many digital encoding schemes are dependent upon the

difference in the propagation delay times of the driver and

the receiver. Using the test circuit of Figure 13, Figures 11

and 12 show the typical LTC485 receiver propagation

delay.

The receiver delay times are:

⏐tPLH – tPHL⏐ = 9ns Typ, VCC = 5V

The driver skew times are:

Skew = 5ns Typ, VCC = 5V

10ns Max, VCC = 5V, TA = – 40°C to 85°C

A

DRIVER

OUTPUTS

B

RECEIVER

OUTPUT

RO

Figure 11. Receiver tPHL

LTC485 • F11

A

DRIVER

OUTPUTS

B

RECEIVER

OUTPUT

RO

Figure 12. Receiver tPLH

LTC485 • F12

TTL IN D

tr, tf < 6ns

100pF

R

100Ω

100pF

BR

R

LTC485 • F13

RECEIVER

OUT

Figure 13. Receiver Propagation Delay Test Circuit

8

sn485 LTC485ffs

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