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LTC4221CGN

Dual Hot Swap Controller/Power Sequencer with Dual Speed, Dual Level Fault Protection

Linear Technology 

LTC4221

TYPICAL PERFOR A CE CHARACTERISTICS

IFAULT(UP) vs Temperature

–3.1

VCC2 = 1V

–3.3 VFAULT = 1.5V

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

–3.5

–3.7

–3.9

–4.1

–4.3

–4.5

–50 –25

0 25 50 75 100 125

TEMPERATURE (°C)

4221 G34

VPWRGD(OL)/VFAULT(OL)

vs Temperature

0.500

0.450

0.400

0.350

VCC2 = 1V, IPWRGD/IFAULT = 1.6mA

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

0.300

0.250

0.200

0.150

0.100

0.050

0

–50 –25

0 25 50 75 100 125

TEMPERATURE (°C)

4221 G37

VFAULT(TH) vs VCC1

0.860

0.855

0.850

RISING

VCC2 = 1V

TA = 25°C

0.845

0.840

0.835

0.830

0.825

0.820

0.815

FALLING

0.810

0 2 4 6 8 10 12 14 16

VCC1 (V)

4221 G35

tp(SC-FAULT) vs Temperature

18

VCC2 = 1V

TIMER = 0.5V

17

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

16

15

14

13

12

–50 –25

0 25 50 75

TEMPERATURE (°C)

100 125

4221 G38

VFAULT(TH) vs Temperature

0.87

VCC1 = 5V

0.86 VCC2 = 3.3V

RISING

0.85

0.84

0.83

0.82

FALLING

0.81

0.80

–50 –25

0 25 50 75

TEMPERATURE (°C)

100 125

4221 G36

tp(FC-GATE) vs Temperature

1.8

VCC2 = 1V

TIMER = 0.5V

1.6

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

1.4

1.2

1.0

0.8

0.6

–50 –25

0 25 50 75

TEMPERATURE (°C)

100 125

4221 G39

PI FU CTIO S

ON1 (Pin 1): System/Channel 1 On Input. Both GATE pins

are pulled low by internal 100μA pull-downs and the

FAULT latch is reset when VON1 < 0.4V. When 0.425V <

VON1 < 0.821V, the FAULT latch is released from reset.

When VON1 > 0.851V, GATE1 ramps up after an initial

timing cycle.

VCC1 (Pin 2): Channel 1 Positive Supply Input. It powers

all the internal circuitry. VCC1 can range from 2.7V to 13.5V

for normal operation but it must be ≥VCC2. An undervolt-

age lockout circuit disables both channels whenever the

voltage at VCC1 is less than 2.5V.

8

SENSE1 (Pin 3): Channel 1 Current Sense Input. A sense

resistor RSENSE1 is placed in the supply path between VCC1

and SENSE1 to sense channel 1 load current. If VRSENSE1

exceeds 100mV for more than 1μs or 25mV for an adjust-

able time (set by the CFILTER), the FAULT latch is set and

fast pull-down circuits are triggered to discharge both

GATEs low. During the start-up cycle, GATE1 ramp-up is

controlled to servo VRSENSE1 ≤ VSENSE(ACL). VSENSE(ACL)

increases from 9mV to 25mV as VFB1 ramps from 0V to

0.5V. To disable the current limit and circuit breaker

function for channel 1, tie SENSE1 to VCC1.

4221fa

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