LTC4210 Ver la hoja de datos (PDF) - Linear Technology
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LTC4210 Datasheet PDF : 20 Pages
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LTC4210-1/LTC4210-2
APPLICATIO S I FOR ATIO
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance CGATE also
determines the GATE start-up as in Equation 6. The CGATE
should be kept below 0.15µF at high supply operation as
the capacitive energy ( 0.5 • CGATE • VGATE2 ) is discharged
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is servoing during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, CTIMER. There are two comparator
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
5µA pull-up
60µA pull-up
2µA pull-down
100µA pull-down
The 100µA is a nonideal current source approximating a
7k resistor below 0.4V.
ends. The 100µA current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
CTIMER by equation:
tINITIAL ≈ 272.9 • CTIMER ms/µF
(5)
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
12
34 5
6
7
>2.5V
VIN
VON
VTIMER
VGATE
>1.3V
5µA
COMP2
100µA
COMP1
10µA
VTH
VOUT
RESET
MODE
INITIAL START-UP NORMAL
CYCLE CYCLE
CYCLE
DISCHARGE
BY LOAD
4210 F03
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply VIN at time
point 1 of Figure 3. The LTC4210 is in reset mode as the
ON pin is low. GATE is pulled low and the TIMER pin is
pulled low with a 100µA source. At time point 2, the short
pin makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5µA. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
Figure 3. Normal Operating Sequence
Start-Up Cycle Without Current Limit
The GATE is released with a 10µA pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold VTH and VOUT starts to follow the GATE
ramp up. If the RSENSE current is below the current limit,
the GATE ramps at a constant rate of:
∆VGATE = IGATE
∆T CGATE
(6)
where CGATE is the total capacitance at the GATE pin.
421012f
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