LTC4210 Ver la hoja de datos (PDF) - Linear Technology

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Fabricante

LTC4210

Hot Swap Controller in 6-Lead SOT-23 Package

Linear Technology 

LTC4210-1/LTC4210-2

APPLICATIO S I FOR ATIO

If a 7mΩ sense resistor with ±1% tolerance is used for

current limiting, the nominal current limit is 7.14A. From

Equations 2 and 3, ILIMIT(MIN) = 6.22A and ILIMIT(MAX) =

8.08A. For proper operation, the minimum current limit

must exceed the circuit maximum operating load current

with margin. The sense resistor power rating must exceed

VCB(MAX)2/RSENSE(MIN).

Frequency Compensation

A compensation circuit should be connected to the GATE

pin for current limit loop stability.

Method 1

The simplest frequency compensation network consists

of RC and CC (Figure 2a). The total GATE capacitance is:

CGATE = CISS + CC

(4)

Generally, the compensation value in Figure 2a is suffi-

cient for a pair of input wires less than a foot in length.

Applications with longer input wires may require the RC or

CC value to be increased for better fault transient perfor-

mance. For a pair of three foot input wires, users can start

with CC = 47nF and RC = 100Ω. Despite the wire length, the

general rule for AC stability required is CC ≥ 8nF and RC ≤

1kΩ.

Method 2

The compensation network in Figure 2b is similar to the

circuitry used in method 1 but with an additional gate re-

sistor RG. The RG resistor helps to minimize high frequency

parasitic oscillations frequently associated with the power

MOSFET. In some applications, the user may find that RG

helps in short-circuit transient recovery as well. However,

too large of an RG value will slow down the turn-off time.

The recommended RG range is between 5Ω and 500Ω.

Usually, method 2 is preferred when the input supply volt-

age is greater than 10V. RG limits the current flow into the

GATE pin’s internal zener clamp during transient events.

The recommended RC and CC values are the same as

method 1. The parasitic compensation capacitor CP is

required when 0.2µF < load capacitance CL < 9µF, other-

wise it is optional.

Parasitic MOSFET Oscillation

There are two possible parasitic oscillations when the

MOSFET operates as a source follower when ramping at

power-up or during current limiting. The first type of os-

cillation occurs at high frequencies, typically above 1MHz.

This high frequency oscillation is easily damped with RG as

mentioned in method 2.

The second type of oscillation occurs at frequencies be-

tween 200kHz and 800kHz due to the load capacitance

being between 0.2µF and 9µF, the presence of RG and RC

resistance, the absence of a drain bypass capacitor, a com-

bination of bus wiring inductance and bus supply output

impedance. There are several ways to prevent this second

type of oscillation. The simplest way is to avoid load ca-

pacitance below 10µF, the second choice is connecting an

external CP > 1.5nF.

RSENSE

Q1

VIN

5V

0.007Ω

Si4410DY

+

VOUT

6

5

CL

VCC SENSE

LTC4210*

4

GATE

RC

100Ω

*ADDITIONAL DETAILS

OMITTED FOR CLARITY

**USE CP IF 0.2µF < CL < 9µF,

OTHERWISE NOT REQUIRED

CC

10nF

(2a)

Method 1

RSENSE

Q1

VIN

0.007Ω

Si4410DY

12V

+

VOUT

6

5

CL

VCC SENSE

LTC4210*

4

GATE

RG

200Ω

CP**

2.2nF

RC

100Ω

(2b)

CC

10nF

4210 F02

Method 2

Figure 2. Frequency Compensation

421012f

10

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