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LTC2914

Quad UV/OV Positive/Negative Voltage Monitor

Linear Technology 

LTC2914

PIN FUNCTIONS

DIS (Pin 13, LTC2914-2): Output Disable Input. Disables

the OV and UV output pins. When DIS is pulled high, the

OV and UV pins are not asserted except during a UVLO

condition. Pin has a weak (2μA) internal pull-down to GND.

Leave pin open if unused.

Exposed Pad (Pin 17, DFN Package): Exposed Pad may

be left open or connected to device ground.

GND (Pin 9): Device Ground

LATCH (Pin 13, LTC2914-1): OV Latch Clear/Bypass Input.

When pulled low, OV is latched when asserted. When

pulled high, OV latch is cleared. While held high, OV has

the same delay and output characteristics as UV.

OV (Pin 11): Overvoltage Logic Output. Asserts low when

any positive polarity input voltage is above threshold or

any negative polarity input voltage is below threshold.

Latched low (LTC2914-1). Held low for an adjustable

delay time after all inputs are valid (LTC2914-2). Pin has

a weak pull-up to VCC and may be pulled above VCC using

an external pull-up. Leave pin open if unused.

REF (Pin 10): Buffered Reference Output. 1V reference

used for the offset of negative-monitoring applications.

The buffered reference sources and sinks up to 1mA. The

reference drives capacitive loads up to 1nF. Larger capacitive

loads may cause instability. Leave pin open if unused.

SEL (Pin 14): Input Polarity Select Three-State Input.

Connect to VCC, GND or leave unconnected in open state

to select one of three possible input polarity combinations

(refer to Table 1).

TMR (Pin 15): Reset Delay Timer. Attach an external

capacitor (CTMR) of at least 10pF to GND to set a reset

delay time of 9ms/nF. A 1nF capacitor will generate an

8.5ms reset delay time. Tie pin to VCC to bypass timer.

UV (Pin 12): Undervoltage Logic Output. Asserts low when

any positive polarity input voltage is below threshold or

any negative polarity input voltage is above threshold.

Held low for an adjustable delay time after all voltage

inputs are valid. Pin has a weak pull-up to VCC and may

be pulled above VCC using an external pull-up. Leave pin

open if unused.

VCC (Pin 16): Supply Voltage. Bypass this pin to GND with

a 0.1μF (or greater) capacitor. Operates as a direct supply

input for voltages up to 6V. Operates as a shunt regulator for

supply voltages greater than 6V and must have a resistance

between the pin and the supply to limit input current to no

greater than 10mA. When used without a current-limiting

resistance, pin voltage must not exceed 6V.

VH1/VH2 (Pin 1/Pin 3): Voltage High Inputs 1 and 2. When

the voltage on this pin is below 0.5V, an undervoltage

condition is triggered. Tie pin to VCC if unused.

VH3/VH4 (Pin 5/Pin 7): Voltage High Inputs 3 and 4. The

polarity of the input is selected by the state of the SEL pin

(refer to Table 1). When the monitored input is configured

as a positive voltage, an undervoltage condition is trig-

gered when the pin is below 0.5V. When the monitored

input is configured as a negative voltage, an overvoltage

condition is triggered when the pin is below 0.5V. Tie pin

to VCC if unused.

VL1/VL2 (Pin 2/Pin 4): Voltage Low Inputs 1 and 2. When

the voltage on this pin is above 0.5V, an overvoltage condi-

tion is triggered. Tie pin to GND if unused.

VL3/VL4 (Pin 6/Pin 8): Voltage Low Inputs 3 and 4. The

polarity of the input is selected by the state of the SEL pin

(refer to Table 1). When the monitored input is configured

as a positive voltage, an overvoltage condition is triggered

when the pin is above 0.5V. When the monitored input is

configured as a negative voltage, an undervoltage condi-

tion is triggered when the pin is above 0.5V. Tie pin to

GND if unused.

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