LTC2282IUP Ver la hoja de datos (PDF) - Linear Technology

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Fabricante

LTC2282IUP

Dual 12-Bit, 105Msps Low Power 3V ADC

Linear Technology 

LTC2282

PIN FUNCTIONS

SHDNA (Pin 59): Channel A Shutdown Mode Selection

Pin. Connecting SHDNA to GND and OEA to GND results

in normal operation with the outputs enabled. Connecting

SHDNA to GND and OEA to VDD results in normal operation

with the outputs at high impedance. Connecting SHDNA

to VDD and OEA to GND results in nap mode with the

outputs at high impedance. Connecting SHDNA to VDD

and OEA to VDD results in sleep mode with the outputs

at high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both

channels. Connecting MODE to GND selects offset binary

output format and turns the clock duty cycle stabilizer

off. 1/3 VDD selects offset binary output format and turns

the clock duty cycle stabilizer on. 2/3 VDD selects 2’s

complement output format and turns the clock duty cycle

stabilizer on. VDD selects 2’s complement output format

and turns the clock duty cycle stabilizer off.

VCMA (Pin 61): Channel A 1.5V Output and Input Common

Mode Bias. Bypass to ground with a 2.2μF ceramic chip

capacitor. Do not connect to VCMB.

SENSEA (Pin 62): Channel A Reference Programming Pin.

Connecting SENSEA to VCMA selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input

range of ±VSENSEA. ±1V is the largest valid input range.

Exposed Pad (Pin 65): ADC Power Ground. The Exposed

Pad on the bottom of the package needs to be soldered

to ground.

FUNCTIONAL BLOCK DIAGRAM

AIN+

INPUT

AIN–

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

VCM

2.2μF

1.5V

REFERENCE

RANGE

SELECT

REF

SENSE

BUF

SHIFT REGISTER

AND CORRECTION

REFH

REFL INTERNAL CLOCK SIGNALS

DIFF

CLOCK/DUTY

CONTROL

REF

CYCLE

LOGIC

AMP

CONTROL

REFH 0.1μF REFL

2.2μF

1μF

1μF

CLK

MODE SHDN

OE

Figure 1. Functional Block Diagram (Only One Channel is Shown)

OUTPUT

DRIVERS

OVDD

OF

D11

•

•

•

D0

OGND

2282 F01

2282fb

9

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