LTC2246LX(RevB) Ver la hoja de datos (PDF) - Linear Technology

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Fabricante

LTC2246LX
(Rev.:RevB)

14-Bit, 25Msps 125°C ADC In LQFP

Linear Technology 

LTC2246H

PIN FUNCTIONS

GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37,

48): ADC Power Ground.

AIN+ (Pin 2): Positive Differential Analog Input.

AIN– (Pin 3): Negative Differential Analog Input.

REFH (Pins 5, 6): ADC High Reference. Bypass to Pins 7,

8 with a 0.1μF ceramic chip capacitor as close to the pin

as possible. Also bypass to Pins 7, 8 with an additional

2.2μF ceramic chip capacitor and to ground with a 1μF

ceramic chip capacitor.

REFL (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6

with a 0.1μF ceramic chip capacitor as close to the pin

as possible. Also bypass to Pins 5, 6 with an additional

2.2μF ceramic chip capacitor and to ground with a 1μF

ceramic chip capacitor.

VDD (Pins 10, 11, 12, 46, 47): 3V Supply. Bypass to GND

with 0.1μF ceramic chip capacitors.

CLK (Pin 14): Clock Input. The input sample starts on the

positive edge.

SHDN (Pin 16): Shutdown Mode Selection Pin. Connecting

SHDN to GND and OE to GND results in normal operation

with the outputs enabled. Connecting SHDN to GND and

OE to VDD results in normal operation with the outputs at

high impedance. Connecting SHDN to VDD and OE to GND

results in nap mode with the outputs at high impedance.

Connecting SHDN to VDD and OE to VDD results in sleep

mode with the outputs at high impedance.

If the clock duty cycle stabilizer is used, a >1μs high pulse

should be applied to the SHDN pin once the power supplies

are stable at power up.

OE (Pin 17): Output Enable Pin. Refer to SHDN pin

function.

D0-D13 (Pins 19-23, 26-28, 33-35, 38-40): Digital Out-

puts. D13 is the MSB.

OGND (Pin 30): Output Driver Ground.

OVDD (Pin 31): Positive Supply for the Output Drivers.

Bypass to ground with 0.1μF ceramic chip capacitor.

OF (Pin 41): Over/Under Flow Output. High when an over

or under flow has occurred.

MODE (Pin 42): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to GND selects

offset binary output format and turns the clock duty cycle

stabilizer off. 1/3 VDD selects offset binary output format

and turns the clock duty cycle stabilizer on. 2/3 VDD selects

2’s complement output format and turns the clock duty

cycle stabilizer on. VDD selects 2’s complement output

format and turns the clock duty cycle stabilizer off.

SENSE (Pin 43): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 44, 45): 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2μF ceramic chip

capacitor.

2246hfb

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