LTC1857 Ver la hoja de datos (PDF) - Linear Technology
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LTC1857 Datasheet PDF : 22 Pages
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LTC1857/LTC1858/LTC1859
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
fSAMPLE(MAX) Maximum Sampling Frequency
tCONV
tACQ
Conversion Time
Acquisition Time
fSCK
SCK Frequency
tr
SDO Rise Time
tf
SDO Fall Time
t1
CONVST High Time
t2
CONVST to BUSY Delay
t3
SCK Period
t4
SCK High
t5
SCK Low
t6
Delay Time, SCK↓ to SDO Valid
t7
Time from Previous SDO Data Remains
Valid After SCK↓
t8
SDO Valid After RD↓
t9
RD↓ to SCK Setup Time
t10
SDI Setup Time Before SCK↑
t11
SDI Hold Time After SCK↑
t12
SDO Valid Before BUSY↑
t13
Bus Relinquish Time
CONDITIONS
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
(Note 14)
See Test Circuits
See Test Circuits
CL = 25pF, See Test Circuits
CL = 25pF, See Test Circuits
CL = 25pF, See Test Circuits
CL = 25pF, See Test Circuits
RD = Low, CL = 25pF, See Test Circuits
See Test Circuits
MIN TYP MAX UNITS
l 100
kHz
166
kHz
l
4
5
µs
l
4
µs
1
µs
l
0
20
MHz
6
ns
6
ns
l 40
ns
l
15
30
ns
l 50
ns
l 10
ns
l 10
ns
l
25
45
ns
l
5
20
ns
l
11
30
ns
l 20
ns
l
0
ns
l
7
ns
l
5
20
ns
l
10
30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and
1111 1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes flicker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12: All Specifications in dB are referred to a full-scale ±10V input.
Note 13: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 14: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15: The specification is referred to the ±10V input range.
For more information www.linear.com/LTC1857
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