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LTC1852

8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs

Linear Technology 

LTC1852/LTC1853

APPLICATIONS INFORMATION

The LTC1852/LTC1853 are complete and very flexible

data acquisition systems. They consist of a 10-bit/12-bit,

400ksps capacitive successive approximation A/D con-

verter with a wideband sample-and-hold, a configurable

8-channel analog input multiplexer, an internal reference

and reference buffer amplifier, a 16-bit parallel digital

output and digital control logic, including a programmable

sequencer.

CONVERSION DETAILS

The core analog-to-digital converter in the LTC1852/

LTC1853 uses a successive approximation algorithm and

an internal sample-and-hold circuit to convert an analog

signal to a 10-bit/12-bit parallel output. Conversion start

is controlled by the CS and CONVST inputs. At the start

of the conversion, the successive approximation register

(SAR) is reset. Once a conversion cycle is begun, it cannot

be restarted. During the conversion, the internal differen-

tial capacitive DAC output is sequenced by the SAR from

the most significant bit (MSB) to the least significant bit

(LSB). The outputs of the analog input multiplexer are

connected to the sample-and-hold capacitors (CSAMPLE)

during the acquire phase and the comparator offset is

nulled by the zeroing switches. In this acquire phase, a

minimum delay of 150ns will provide enough time for

the sample-and-hold capacitors to acquire the analog

signal. During the convert phase, the comparator zeroing

switches are open, putting the comparator into compare

mode. The input switches connect CSAMPLE to ground,

transferring the differential analog input charge onto the

summing junction. This input charge is successively

compared with the binary weighted charges supplied by

the differential capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of the conversion,

the differential DAC output balances the input charges.

The SAR contents (a 10-bit/12-bit data word), which

represents the difference of the analog input multiplexer

outputs, and the 4-bit address word are loaded into the

14-bit/16-bit output latches.

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band lim-

ited to frequencies above DC to below half the sampling

frequency. The effective number of bits (ENOBs) is a

measurement of the resolution of an ADC and is directly

related to the S/(N + D) by the equation:

ENOB = [S/(N + D) – 1.76]/6.02

where ENOB is the effective number of bits and S/(N + D) is

expressed in dB. At the maximum sampling rate of 400kHz,

the LTC1852/LTC1853 maintain near ideal ENOBs up to

and beyond the Nyquist input frequency of 200kHz.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

THD = 20Log V22 + V32 + V42 +...Vn2

V1

where V1 is the RMS amplitude of the fundamental

frequency and V2 through Vn are the amplitudes of the

second through nth harmonics. The LTC1852/LTC1853

have good distortion performance up to the Nyquist

frequency and beyond.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

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