LTC1657 Ver la hoja de datos (PDF) - Linear Technology

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LTC1657

Parallel 16-Bit Rail-to-Rail Micropower DAC

Linear Technology 

LTC1657/LTC1657L

PI FU CTIO S

CLR (Pin 27): Clear Input (Asynchronous Active Low). A

low on this pin asynchronously resets all input and DAC

registers to 0s.

LDAC (Pin 28): Load DAC (Asynchronous Active Low).

Used to asynchronously transfer the contents of the input

registers to the DAC register which updates the output

voltage. If held low, the DAC register loads data from the

input registers which will immediately update VOUT.

DIGITAL INTERFACE TRUTH TABLE

CLR

CSMSB CSLSB

WR

L

X

X

X

H

X

X

X

H

X

X

X

H

L

H

L

H

H

L

L

H

L

L

L

H

X

X

H

H

H

X

X

H

X

H

X

H

L

L

L

LDAC

X

L

H

X

X

X

X

X

X

L

FUNCTION

Clears input and DAC registers to zero

Loads DAC register with contents of input registers

Freezes contents of DAC register

Writes MSB byte into MSB input register

Writes LSB byte into LSB input register

Writes MSB and LSB bytes into MSB and LSB input registers

Inhibits write to MSB and LSB input registers

Inhibits write to MSB input register

Inhibits write to LSB input register

Data bus flows directly through input and DAC registers

TIMING DIAGRAM

CSLSB

CSMSB

WR

LDAC

DATA

t CS

t CWS

t WR

t CWH

t DWS

t DWH

DATA VALID

t CS

t WR

DATA VALID

t LDAC

DAC UPDATE

1657 TD

8

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