LTC1650 Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

Fabricante

LTC1650

Low Glitch 16-Bit Voltage Output DAC

Linear Technology 

U

OPERATIO

Serial Interface

The data on the DIN input is loaded into the shift register

on the rising edge of the clock. Data is loaded as one

16-bit word, MSB first. The DAC register loads the data

from the shift register when CS/LD is pulled high. The

clock is disabled internally when CS/LD is high. Note: CLK

must be low before CS/LD is pulled low to avoid an extra

internal clock pulse.

The buffered output of the 16-bit shift register is available

on the DOUT pin which swings from DGND to DVDD.

Multiple LTC1650s may be daisy-chained together by

connecting the DOUT pin to the DIN pin of the next chip

while the clock and CS/LD signals remain common to all

chips in the daisy chain. The serial data is clocked to all of

the chips, then the CS/LD signal is pulled high to update all

of them simultaneously.

When CLR is pulled low or when the part powers up, the

output connects through an internal pass gate to VRST and

will go to whatever voltage is on VRST. When any of three

supplies (DVDD, AVDD, |AVSS|) goes below 2.5V, the

RSTOUT pin goes low and stays low as long as the supply

is below 2.5V. The power-on reset is also activated when

one of the supplies drops below 2.5V and the output is

then connected to VRST. The output connects to VRST

when any of three conditions occur: CLR goes low, the part

powers up or one of the supplies drops below 2.5V. This

LTC1650

condition exists as long as CS/LD is low. As soon as CS/LD

goes high, the DAC register is loaded with the data in the

shift register and the output will settle to its new value.

Voltage Output

The LTC1650 rail-to-rail buffered output can source or

sink 5mA over the entire operating temperature range. The

output is specified to swing up to ±4.5V on ±4.75V

supplies with VOUT unloaded. (For typical output swing at

various load currents, refer to the typical curve “Minimum

Supply Headroom for Full Output Swing vs Load Cur-

rent.”) The buffer amplifier can drive 1000pF without

going into oscillation. The LTC1650 has a deglitched

voltage output. The midscale glitch is less than 2nV-s. The

digital feedthrough is about 0.05nV-s.

Output Ranges

The LTC1650 is capable of unipolar or bipolar output

swing. When the UNI/BIP pin is connected to VOUT the part

is configured for unipolar operation and the output will

swing from REFLO to REFHI. When UNI/BIP is connected

to REFHI the part is configured in bipolar mode and the

output will swing from (2 • REFLO – REFHI) to REFHI and

will be at REFLO at midscale. With REFLO = 0V the output

swing is ±REFHI in bipolar mode and 0V to REFHI in

unipolar mode.

9

Share Link: