LTC1422 Ver la hoja de datos (PDF) - Linear Technology

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LTC1422

Hot Swap Controller

Linear Technology 

LTC1422

APPLICATIONS INFORMATION

1

V2

VOUT

TIMER

2

3

4

V1 V2

V1 V2

1.232V

1.232V

1 30µs 2

ON

TIMER

15µs

3 30µs 4 5 6

RESET

1422 F04

Figure 4. Supply Monitor Waveforms

When the voltage at the FB pin rises above its reset

threshold (1.232V), the comparator COMP 2 output goes

high, and a timing cycle starts (Figure 4, time points 1 and

4). After a complete timing cycle, RESET is pulled high.

The 12µA pull-up current source to VCC on RESET has a

series diode so the pin can be pulled above VCC by an

external pull-up resistor without forcing current back into

supply.

When the supply voltage at the FB pin drops below its reset

threshold, the comparator Comp 2 output goes low. After

passing through a glitch filter, RESET is pulled low (time

point 2). If the FB pin rises above the reset threshold for

less than a timing cycle, the RESET output will remain low

(time point 3).

Glitch Filter

The LTC1422 has a glitch filter to prevent RESET from

generating a system reset when there are transients on the

FB pin. The filter is 20µs for large transients (greater than

150mV) and up to 80µs for small transients. The relation-

ship between glitch filter time and the transient voltage is

shown in Typical Performance curve: Glitch Filter Time vs

Feedback Transient.

Soft Reset

In some cases a system reset is desired without a power

down. The ON pin can signal the RESET pin to go low

without turning off the external N-channel (a soft reset).

This is accomplished by holding the ON pin low for only

15µs or less (Figure 5, time point 1). At about 30µs from

the falling edge of the ON pin (time point 2) the RESET pin

goes low and stays low for one timing cycle.

GATE

VOUT

RESET

20µs

1422 F05

Figure 5. Soft Reset Waveforms

If the ON pin is held low for longer than 40µs, the gate will

turn off and the RESET pin will eventually go low (time

points 4, 5 and 6).

Timer

The system timing for the LTC1422 is generated by the

circuitry shown in Figure 6. The timer is used to set the

turn-on delay after the ON pin goes high and the delay

before the RESET pin goes high after the output supply

voltage is good as sensed by the FB pin.

R1

Q2

VCC

R2

+ VOUT

CLOAD

LTC1422

2

ON

2µA

1.232V

8

7

6

VCC SENSE GATE

LOGIC

+

COMP 4

–

C1

SUPPLY

MONITOR

Q1

TIMER

3

4

C2

R3

5

R4

1

RESET

1422 F06

Figure 6. System Timing Block Diagram

8

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