LTC1421(Rev_A) Ver la hoja de datos (PDF) - Linear Technology
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LTC1421 Datasheet PDF : 24 Pages
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LTC1421/LTC1421-2.5
TYPICAL PERFORMANCE CHARACTERISTICS
CPON Voltage vs Source Current
(Charge Pump On)
5
VCCLO = 5V
VCCHI = 12V
4
3
2
1
0
0 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 – 3.0
SOURCE CURRENT (mA)
1421 G10
ICCLO Supply Current
vs VCCLO Voltage
7
VCCHI = 12V
6
5
4
3
2
1
0
02
4 6 8 10
VCCLO VOLTAGE (V)
12 14
1421 G11
PIN FUNCTIONS
CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO.
Together with CON2, it is used to indicate board connec-
tion. The pin must be tied to ground on the host side of the
connector. When using staggered connector pins, CON1
and CON2 must be the shortest and must be placed at
opposite corners of the connector. Board insertion is
assumed after CON1 and CON2 are both held low for 20ms
after power-up.
CON2 (Pin 2): TTL Level Input with a Pull-Up to VCCLO.
Together with CON1 it is used to indicate board connec-
tion.
POR (Pin 3): TTL Level Input with a Pull-Up to VCCLO.
When the pin is pulled low for at least 20ms, a hard reset
is generated. Both VOUTLO and VOUTHI will turn off at a
controlled rate. A power-up sequence will not start until
the POR pin is pulled high. If POR is pulled high before
VOUTLO and VOUTHI are fully discharged, a power-up
sequence will not begin until the voltage at VOUTLO and
VOUTHI are below VTRIP. The electronic circuit breaker will
be reset by pulling POR low.
FAULT (Pin 4): Open Drain Output to GND with a Weak
Pull-Up to VCCLO. The pin is pulled low when an overcur-
rent fault is detected at VOUTLO or VOUTHI.
DISABLE (Pin 5): CMOS Output. The signal is used to
disable the board’s data bus during insertion or removal.
PWRGD (Pin 6): Open Drain Output to GND with a Weak
Pull-Up to VCCLO. The pin is pulled low immediately after
VOUTLO falls below its reset threshold voltage. The pin is
pulled high immediately after VOUTLO rises above its reset
threshold voltage.
RESET (Pin 7): Open Drain Output to GND with a Weak
Pull-Up to VCCLO. The pin is pulled low when a reset
condition is detected. A reset will be generated when any
of the following conditions are met: Either CON1 or CON2
is high, POR is pulled low, VCCLO or VCCHI are below their
respective undervoltage lockout thresholds, PWRGD goes
low or an overcurrent fault is detected at VOUTLO or
VOUTHI. RESET will go high 200ms after PWRGD goes
high. On power failure, RESET will go low 32µs after
PWRGD goes low.
REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V
±1%. The reference can source up to 5mA of current. A
1µF bypass capacitor is recommended.
CPON (Pin 9): CMOS Output That Can Be Pulled Below
Ground. CPON is pulled high when the internal charge
pumps for GATELO and GATEHI are turned on. CPON is
pulled low when the charge pumps are turned off. The pin
can be used to control an external MOSFET for a – 5V to
– 12V supply.
5
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