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LTC1294CCSW

Single Chip 12-Bit Data Acquisition System

Linear Technology 

LTC1293/LTC1294/LTC1296

APPLICATI S I FOR ATIO

The LTC 1293/4/6 is a data acquisition component which

contains the following functional blocks:

1. 12-bit successive approximation capacitive A/D

converter

2. Analog multiplexer (MUX)

3. Sample and hold (S/H)

4. Synchronous, half duplex serial interface

5. Control and timing logic

DIGITAL CONSIDERATIONS

Serial Interface

The LTC1293/4/6 communicates with microprocessors

and other external circuitry via a synchronous, half duplex,

four-wire serial interface (see Operating Sequence). The

clock (CLK) synchronizes the data transfer with each bit

being transmitted on the falling CLK edge and captured on

the rising CLK edge in both transmitting and receiving

systems. The input data is first received and then the A/D

conversion result is transmitted (half duplex). Because of

INPUT DATA WORD

The LTC1293/4/6 seven-bit data word is clocked into the

DIN input on the rising edge of the clock after chip select

goes low and the start bit has been recognized. Further

inputs on the DIN pin are then ignored until the next CS

cycle. The input word is defined as follows:

UNIPOLAR/

BIPOLAR

POWER

SHUTDOWN

START

SGL/

DIFF

ODD/

SIGN

SELECT SELECT

1

0

UNI

MSBF

PS

MUX ADDRESS

MSB FIRST/

LSB FIRST LTC1293 AI02

Start Bit

The first "logical one" clocked into the DIN input after CS

goes low is the start bit. The start bit initiates the data

transfer and all leading zeroes which precede this logical

one will be ignored. After the start bit is received the

remaining bits of the input word will be clocked in. Further

inputs on the DIN pin are then ignored until the next CS

cycle.

CS

DIN 1

DOUT 1

DIN 2

DOUT 2

SHIFT MUX 1 NULL SHIFT A/D CONVERSION

ADDRESS IN BIT

RESULT OUT

the half duplex operation DIN and DOUT may be tied

together allowing transmission over just 3 wired: CS, CLK

and DATA (DIN/DOUT). Data transfer is initiated by a falling

chip select (CS) signal. After CS falls the LTC1293/4/6

looks for a start bit. After the start bit is received a 7-bit

input word is shifted into the DIN input which configures

the LTC1293/4/6 and starts the conversion. After one null

bit, the result of the conversion is output on the DOUT line.

With the half duplex serial interface the DOUT data is from

the current conversion. After the end of the data exchange

CS should be brought high. This resets the LTC1293/4/6

in preparation for the next data exchange.

10

LTC1293 AI01

MUX Address

The four bits of the input word following the START BIT

assign the MUX configuration for the requested conver-

sion. For a given channel selection, the converter will

measure the voltage between the two channels indicated

by the + and – signs in the selected row of the following

table. Note that in differential mode (SGL/DIFF = 0) mea-

surements are limited to four adjacent input pairs with

either polarity. In single ended mode, all input channels

are measured with respect to COM. Only the +inputs have

sample and holds. Signals applied at the –inputs must not

change more than the required accuracy during the con-

version.

129346fs

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