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LTC1291BCJ8

Single Chip 12-Bit Data Acquisition System

Linear Technology 

LTC1291

TEST CIRCUITS

Voltage Waveforms for DOUT Rise and Fall Times, tr, tf

Voltage Waveforms for DOUT Delay Time, tdDO

DOUT

tr

2.4V

0.4V

tf

1291 TC04

CLK

DOUT

0.8V

tdDO

2.4V

0.4V

1291 TC03

Voltage Waveforms for ten

CS

DIN

START

CLK

1

2

3

4

5

DOUT

0.8V

ten

B11

1291 TC07

APPLICATI S I FOR ATIO

The LTC1291 is a data acquisition component which

contains the following functional blocks:

1. 12-bit successive approximation capacitive A/D

converter

2. Analog multiplexer (MUX)

3. Sample-and-hold (S/H)

4. Synchronous, half duplex serial interface

5. Control and timing logic

DIGITAL CONSIDERATIONS

Serial Interface

The LTC1291 communicates with microprocessors and

other external circuitry via a synchronous, half duplex,

4-wire serial interface (see Operating Sequence). The

clock (CLK) synchronizes the data transfer with each bit

being transmitted on the falling CLK edge and captured on

the rising CLK edge in both transmitting and receiving

systems.

CS

DIN 1

DOUT 1

DIN 2

DOUT 2

SHIFT MUX 1 NULL SHIFT A/D CONVERSION

ADDRESS IN BIT RESULT OUT

Figure 1

1291 F01

The input data is first received and then the A/D conversion

result is transmitted (half duplex). Because of the half

duplex operation DIN and DOUT may be tied together

allowing transmission over just 3 wires: CS, CLK and

1291fa

7

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