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LTC1267CG-ADJ

Dual High Efficiency Synchronous Step-Down Switching Regulators

Linear Technology 

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OPERATIO (Refer to Functional Diagram)

The LTC1267 series consists of two individual regulator

blocks, each using current mode, constant off-time archi-

tectures to synchronously switch an external pair of

complementary power MOSFETs. The two regulators are

internally set to provide output voltages of 3.3V and 5V for

the LTC1267. The LTC1267-ADJ is configured to provide

two adjustable output voltages, each set by their indi-

vidual external resistor dividers. The LTC1267-ADJ5 has

adjustable and 5V output voltages. Operating frequency is

individually set on each section by the external capacitors

attached to the CT pin.

The output voltage is sensed by an internal voltage divider

connected to the Sense– pin or external divider returned

to the VFB pin (LTC1267-ADJ, LTC1267-ADJ5). A voltage

comparator V and a gain block G compare the divided

output voltage with a reference voltage of 1.25V. To

optimize efficiency, the LTC1267 series automatically

switches between two modes of operation, Burst Mode

and continuous mode. The voltage comparator is the

primary control element when the device is in Burst Mode

operation, while the gain block controls the output voltage

in continuous mode.

A low dropout 4.5V regulator provides the operating

voltage VCC for the MOSFET drivers and control circuitry

during start-up. During normal operation, the LTC1267

family powers the drivers and control from the output via

the EXT VCC pin to improve efficency. The NGate pin is

referenced to ground and drives the N-channel MOSFET

gate directly. The P-channel gate drive must be referenced

to the main supply input VIN, which is accomplished by

level-shifting the PDrive signal via an internal 550k resis-

tor and an external capacitor.

During the switch “ON” cycle in continuous mode, current

comparator C monitors the voltage between Sense+ and

Sense– pins connected across an external shunt in series

with the inductor. When the voltage across the shunt

reaches its threshold value, the PGate output is switched

to VIN, turning off the P-channel MOSFET. The timing

capacitor CT is now allowed to discharge at a rate deter-

mined by the off-time controller. The discharge current is

made proportional to the output voltage to model the

inductor current, which decays at a rate that is also

LTC1267

LTC1267-ADJ/LTC1267-ADJ5

proportional to the output voltage. While the timing ca-

pacitor is discharging, the NGate output is high, turning

on the N-channel MOSFET.

When the voltage on the timing capacitor has discharged

past VTH1, comparator T trips, setting the flip-flop. This

causes the NGate output to go low (turning off the

N-channel MOSFET) and the PGate output to also go low

(turning the P-channel MOSFET back on). The cycle then

repeats. As the load current increases, the output voltage

decreases slightly. This causes the output of the gain

stage to increase the current comparator threshold, thus

tracking the load current.

The sequence of events for Burst Mode operation is very

similar to continuous operation with the cycle interrupted

by the voltage comparator. When the output voltage is at

or above the desired regulated value, the P-channel

MOSFET is held off by comparator V and the timing

capacitor continues to discharge below VTH1. When the

timing capacitor discharges past VTH2, voltage compara-

tor S trips, causing the internal SLEEP line to go low and

the N-channel MOSFET to turn off.

The circuit now enters sleep mode with both power

MOSFETs turned off. In sleep mode a majority of the

circuitry is turned off, dropping the quiescent current

from several mA (with the MOSFETs switching) to 360µA.

The load current is now being supplied by the output

capacitor. When the output voltage has dropped by the

amount of hysteresis in comparator V, the P-channel

MOSFET is again turned on and this process repeats.

To avoid the operation of the current loop interfering with

Burst Mode operation, a built-in offset VOS is incorporated

in the gain stage. This prevents the current comparator

threshold from increasing until the output voltage has

dropped below a minimum threshold.

To prevent both the external MOSFETs from ever being

turned on at the same time, feedback is incorporated to

sense the state of the driver output pins. Before the

NGate output can go high, the PDrive output must also be

high. Likewise, the PDrive output is prevented from going

low while the NGate output is high.

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