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LT3755(RevA) Ver la hoja de datos (PDF) - Linear Technology

Número de pieza
componentes Descripción
Fabricante
LT3755
(Rev.:RevA)
Linear
Linear Technology Linear
LT3755 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LT3755/LT3755-1
PIN FUNCTIONS (MSOP/QFN)
SYNC (Pin 9/Pin 3, LT3755-1 Only): The SYNC pin is used
to synchronize the internal oscillator to an external logic
level signal. The RT resistor should be chosen to program
an internal switching frequency 20% slower than the SYNC
pulse frequency. Gate turn-on occurs a fixed delay after
the rising edge of SYNC. For best PWM performance, the
PWM rising edge should occur at least 200ns before the
SYNC rising edge. Use a 50% duty cycle waveform to
drive this pin. This pin replaces OPENLED on LT3755-1
option parts. If not used, tie this pin to GND.
SS (Pin 10/Pin 4): Soft-Start Pin. This pin modulates
oscillator frequency and compensation pin voltage (VC)
clamp. The soft-start interval is set with an external capaci-
tor. The pin has a 10μA (typical) pull-up current source
to an internal 2.5V rail. The soft-start pin is reset to GND
by an undervoltage condition (detected by SHDN/UVLO
pin) or thermal limit.
RT (Pin 11/Pin 5): Switching Frequency Adjustment Pin.
Set the frequency using a resistor to GND (for resistor
values, see the Typical Performance curve or Table 1). Do
not leave the RT pin open.
SHDN/UVLO (Pin 12/Pin 6): Shutdown and Undervoltage
Detect Pin. An accurate 1.22V falling threshold with ex-
ternally programmable hysteresis detects when power is
OK to enable switching. Rising hysteresis is generated by
the external resistor divider and an accurate internal 2μA
pull-down current. Above the 1.24V (nominal) threshold
(but below 6V), SHDN/UVLO input bias current is sub-μA.
Below the falling threshold, a 2μA pull-down current is
enabled so the user can define the hysteresis with the
external resistor selection. An undervoltage condition
resets soft-start. Tie to 0.4V, or less, to disable the device
and reduce VIN quiescent current below 1μA. Do not tie
SHDN/UVLO to a voltage higher than VIN.
INTVCC (Pin 13/Pin 7): Regulated Supply for Internal Loads,
GATE Driver and PWMOUT Driver. Supplied from VIN and
regulates to 7V (typical). INTVCC must be bypassed with
a 4.7μF capacitor placed close to the pin. Connect INTVCC
directly to VIN if VIN is always less than or equal to 7V.
VIN (Pin 14/Pin 8): Input Supply Pin. Must be locally
bypassed with a 0.22μF (or larger) capacitor placed close
to the IC.
SENSE (Pin 15/Pin 9): The current sense input for the
control loop. Kelvin connect this pin to the positive ter-
minal of the switch current sense resistor, RSENSE, in the
source of the NFET. The negative terminal of the current
sense resistor should be connected to the GND plane
close to the IC.
GATE (Pin 16/Pin 10): N-Channel FET Gate Driver Output.
Switches between INTVCC and GND. Driven to GND during
shutdown, fault or idle states.
Exposed Pad (Pin 17/Pin 17): Ground. This pin also serves
as current sense input for control loop, sensing negative
terminal of current sense resistor. Solder the Exposed Pad
directly to ground plane.
37551fa
8

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