LT3581IMSE-TRPBF Ver la hoja de datos (PDF) - Linear Technology
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LT3581IMSE-TRPBF Datasheet PDF : 36 Pages
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LT3581
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
General Layout Guidelines
• To optimize thermal performance, solder the exposed
ground pad of the LT3581 to the ground plane, with
multiple vias around the pad connecting to additional
ground planes.
• A ground plane should be used under the switcher circuitry
to prevent interplane coupling and overall noise.
• High speed switching path (see specific topology for
more information) must be kept as short as possible.
• The VC, FB, and RT components should be placed as
close to the LT3581 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
• Place the bypass capacitor for the VIN pin as close as
possible to the LT3581.
• Place the bypass capacitor for the inductor as close as
possible to the inductor.
• The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
erning switch, diode D1, output capacitor COUT1, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
erning switch, flying capacitor C1, diode D1, output
capacitor COUT, and ground return as short as possible
to minimize parasitic inductive spikes at the switch node
during switching.
Inverting Topology Specific Layout Guidelines
• Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor COUT’s ground
return path (to chip) in order to minimize switching
noise coupling into the output.
• Keep length of loop (high speed switching path) govern-
ing switch, flying capacitor C1, diode D1, and ground
return as short as possible to minimize parasitic induc-
tive spikes at the switch node during switching.
GND
GND
1
2
3
4
5
CIN
6
A7
–
VIN
8
+
L1
16
SYNC
17
15
14
13
SHDN
12
CLKOUT
11
B
10
9
D1
COUT
COUT1
M1
–
VOUT
+
D2
RGATE
3581 F08
A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT
COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN COUT AND COUT1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE COUT AND COUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
Figure 8. Suggested Component Placement for Boost Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
1
16
SYNC
2
17
15
3
14
4
13
SHDN
5
CIN
6
12
CLKOUT
11
7
A8
–
•
10
B
9
–
VIN
+
D1
L2
C1
L1 •
COUT
VOUT
+
3581 F09
A: RETURN CIN AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN COUT GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED
PERFORMANCE.
Figure 9. Suggested Component Placement for SEPIC Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
3581fb
16
For more information www.linear.com/LT3581
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