LT3581IMSE-TRPBF Ver la hoja de datos (PDF) - Linear Technology
Número de pieza
componentes Descripción
Fabricante
LT3581IMSE-TRPBF Datasheet PDF : 36 Pages
| |||
LT3581
PIN FUNCTIONS (DFN/MSOP)
FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For
a Boost or Inverting Converter, tie a resistor from the FB
pin to VOUT according to the following equations:
RFB
=
VOUT – 1.215V
83.3•10–6
;
Boost
or
SEPIC
Converter
RFB
=
|
VOUT | + 9mV
83.3•10–6
; Inverting
Converter
VC (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external
compensation network to this pin.
GATE (Pin 3/Pin 3): PMOS Gate Drive Pin. The GATE pin
is a pull-down current source, used to drive the gate of
an external PMOS for output short circuit protection or
output disconnect. The GATE pin current increases linearly
with the SS pin’s voltage, with a maximum pull-down
current of 933µA at SS voltages exceeding 500mV. Note
that if the SS voltage is greater than 500mV and the GATE
pin voltage is less than 2V, then the GATE pin looks like
a 2kΩ impedance to ground. See the Appendix for more
information.
FAULT (Pin 4/Pin 4): Fault Indication Pin. This active low,
bidirectional pin can either be pulled low (below 750mV)
by an external source, or internally by the chip to indicate a
fault. When pulled low, this pin causes the power switches
to turn off, the GATE pin to become high impedance, the
CLKOUT pin to become disabled, and the SS pin to go
through a charge/discharge sequence. The end/absence
of a fault is indicated when the voltage on this pin exceeds
1V. A pull-up resistor or current source is needed on this
pin to pull it above 1V in the absence of a fault.
VIN (Pin 5/Pin 5): Input Supply Pin. Must be locally by-
passed.
SW1 (Pins 6, 7/Pins 6,7, 8): Master Switch Pin. This is the
collector of the internal master NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI.
SW2 (Pins 8, 9/Pins 9, 10, 11): Slave Switch Pin. This
is the collector of the internal slave NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI.
CLKOUT (Pin 10/Pin 12): Clock Output Pin. Use this pin
to synchronize one or more other compatible switching
regulator ICs to the LT3581. The clock that this pin outputs
runs at the same frequency as the internal oscillator of the
part or as the SYNC pin. CLKOUT may also be used as a
temperature monitor since the CLKOUT pin’s duty cycle
varies linearly with the part’s junction temperature. Note
that the CLKOUT pin is only meant to drive capacitive
loads up to 50pF.
SHDN (Pin 11/Pin 13): Shutdown Pin. In conjunction
with the UVLO (undervoltage lockout) circuit, this pin is
used to enable/disable the chip and restart the soft-start
sequence. Drive below 300mV to disable the chip. Drive
above 1.33V (typical) to activate the chip and restart the
soft-start sequence. Do not float this pin.
RT (Pin 12/Pin 14): Timing Resistor Pin. Adjusts the
LT3581’s switching frequency. Place a resistor from this
pin to ground to set the frequency to a fixed free running
level. Do not float this pin.
SS (Pin 13/Pin 15): Soft-Start Pin. Place a soft-start
capacitor here. Upon start-up, the SS pin will be charged
by a (nominally) 250k resistor to about 2.1V. During a
fault, the SS pin will be slowly charged up and eventually
discharged as part of a timeout sequence (see the State
Diagram for more information on the SS pin’s role during
a fault event).
SYNC (Pin 14/Pin 16): To synchronize the switching
frequency to an outside clock, simply drive this pin with
a clock. The high voltage level of the clock must exceed
1.3V, and the low level must be less than 0.4V. Drive this
pin to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.
GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Ground.
Exposed pad must be soldered directly to local ground
plane.
For more information www.linear.com/LT3581
3581fb
7
Share Link: 