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LT3580EDD-TRPBF

Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization

Linear Technology 

LT3580

APPLICATIONS INFORMATION

so they should not be used for calculating efficiency in

discontinuous mode or at light load currents.

Average Input Current:

IIN

=

VOUT

VIN

• IOUT

•η

Switch I2R Loss: PSW = (DC)(IIN)2(RSW )

Base Drive Loss (AC): PBAC = 13n(IIN)(VOUT )(f)

Base Drive Loss (DC):

PBDC

=

(VIN

)(IIN )(DC)

50

Input Power Loss: PINP = 7mA(VIN)

where:

RSW = switch resistance (typically 200mΩ at 1.5A)

DC = duty cycle (see the Power Switch Duty Cycle sec-

tion for formulas)

η = power conversion efficiency (typically 88% at high

currents)

Example: boost configuration, VIN = 5V, VOUT = 12V,

IOUT = 0.5A, f = 1.25MHz, VD = 0.5V:

IIN = 1.36A

DC = 61.5%

PSW = 228mW

PBAC = 270mW

PBDC = 84mW

PINP = 35mW

Total LT3580 power dissipation (PTOT) = 617mW

Thermal resistance for the LT3580 is influenced by the pres-

ence of internal, topside or backside planes. To calculate

die temperature, use the appropriate thermal resistance

number and add in worst-case ambient temperature:

TJ = TA + θJA • PTOT

where TJ = junction temperature, TA = ambient tempera-

ture, θJA = 43°C/W for the 3mm × 3mm DFN package and

35°C/W to 40°C/W for the MSOP Exposed Pad package.

PTOT is calculated above.

VIN Ramp Rate

While initially powering a switching converter application,

the VIN ramp rate should be limited. High VIN ramp rates can

cause excessive inrush currents in the passive components

of the converter. This can lead to current and/or voltage

overstress and may damage the passive components or

the chip. Ramp rates less than 500mV/μs, depending on

component parameters, will generally prevent these issues.

Also, be careful to avoid hot-plugging. Hot-plugging occurs

when an active voltage supply is “instantly” connected or

switched to the input of the converter. Hot-plugging results

in very fast input ramp rates and is not recommended.

Finally, for more information, refer to Linear application

note AN88, which discusses voltage overstress that can

occur when an inductive source impedance is hot-plugged

to an input pin bypassed by ceramic capacitors.

Layout Hints

As with all high frequency switchers, when considering

layout, care must be taken to achieve optimal electrical,

thermal and noise performance. One will not get adver-

tised performance with a careless layout. For maximum

efficiency, switch rise and fall times are typically in the

5ns to 10ns range. To prevent noise, both radiated and

conducted, the high speed switching current path, shown in

Figure 8, must be kept as short as possible. This is imple-

mented in the suggested layout of a boost configuration in

Figure 9. Shortening this path will also reduce the parasitic

trace inductance. At switch-off, this parasitic inductance

produces a flyback spike across the LT3580 switch. When

operating at higher currents and output voltages, with poor

layout, this spike can generate voltages across the LT3580

that may exceed its absolute maximum rating. A ground

plane should also be used under the switcher circuitry to

prevent interplane coupling and overall noise.

The VC and FB components should be kept as far away

as practical from the switch node. The ground for these

components should be separated from the switch cur-

rent path. Failure to do so can result in poor stability or

subharmonic oscillation.

3580fg

15

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