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LT3482EUD Ver la hoja de datos (PDF) - Linear Technology

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LT3482EUD Datasheet PDF : 12 Pages
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LT3482
PI FU CTIO S
APD (Pin 2): Connect APD cathode to this pin.
MONIN (Pin 3): Current Monitor Power Supply Pin. An
external lowpass filter can be included here to further
reduce supply voltage ripple.
VOUT2 (Pin 4): Voltage Doubler Output Pin. Put a 50V
rated capacitor between this pin and VOUT1. Tie a resistor
divider to the FB pin and GND.
VOUT1 (Pin 5): Boost Output Pin. Put a capacitor between
this pin and the GND plane. Minimize the length of the
trace to the capacitor.
PUMP (Pin 6): Charge Pump Pin. Put a 50V rating bypass
capacitor between SW and PUMP to form a complete volt-
age doubler with the internal integrated Schottky diodes.
Minimize trace length to the capacitor.
SW (Pins 7, 8): Switch Pin. Minimize the trace length on
this pin to reduce EMI.
GND (Pins 9, 10): Ground. Pins connected internally. For
best performance, connect both pins to board ground.
VIN (Pin 11): Input Supply Pin. This pin must be locally
bypassed.
SHDN (Pin 12): Shutdown Pin. Tie to 1.5V or higher to
enable device; 0.4V or less to disable device. This pin also
functions as soft-start between 1.5V and 2V.
CTRL (Pin 13): Internal Reference Override Pin. This allows
the FB voltage to be externally set between 0V and 1.2V.
Tie this pin higher than 1.5V to use the internal reference
of 1.235V.
FB (Pin 14): Feedback Pin. Connect the output resistor
divider tap here.
fSET (Pin 15): Oscillator Frequency Selection Pin. Tie this
pin to above 1.5V or higher to select the higher switching
frequency of 1.1MHz. For lower switching frequency, tie
to GND.
MON (Pin 16): Current Monitor Output Pin. It sources a
current equal to 20% of the APD current and converts to
a reference voltage through an external resistor.
Exposed Pad (Pin 17): GND. This pin must be soldered
to the PCB.
3482fa
5

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