LT3070 Ver la hoja de datos (PDF) - Linear Technology

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LT3070

5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator

Linear Technology 

LT3070

PIN FUNCTIONS

MARGSEL (Pin 21): Margining Enable and Polarity Se-

lection. This three-state pin determines both the polarity

and the active state of the margining function. The logic

low threshold is less than 220mV referenced to GND and

enables negative voltage margining. The logic “high”

threshold is greater than VBIAS – 500mV and enables

positive voltage margining. The voltage range between

these two logic thresholds defines the logic Hi-Z state

and disables the margining function.

MARGTOL (Pin 22): Margining Tolerance. This three-

state pin selects the absolute value of margining (1%,

3% or 5%) if enabled by the MARGSEL input. The logic

low threshold is less than 220mV referenced to GND and

enables either ±1% change in VOUT depending on the state

of the MARGSEL pin. The logic high threshold is greater

than VBIAS – 500mV and enables either ±5% change in

VOUT depending on the state of the MARGSEL pin. The

voltage range between these two logic thresholds defines

the logic Hi-Z state and enables either ±3% change in VOUT

depending on the state of the MARGSEL pin.

VO2, VO1 and VO0 (Pins 23, 24, 25): Output Voltage Select.

These three-state pins combine to select a nominal output

voltage from 0.8V to 1.8V in increments of 50mV. Output

voltage is limited to 1.8V maximum by an internal override

of VO1 when VO2 = “1”. The input logic “0” threshold is less

than 220mV referenced to GND and the logic “1” threshold

is greater than VBIAS – 500mV. The range between these

two thresholds defines the logic Hi-Z state. See Table 1 in

the Applications Information section that defines the VO2,

VO1 and VO0 settings versus VOUT.

BIAS (Pin 27): Bias Supply. This pin supplies current

to most of the internal control circuitry and the output

stage driving the pass transistor. The LT3070 requires a

minimum 2.2μF bypass capacitor for stability and proper

operation. To ensure proper operation, the BIAS voltage

must conform to the equation:

(1.2 • VOUT) + 935mV ≤ VBIAS ≤ 3.6V

EN (Pin 28): Enable. This pin starts the internal reference,

enables all outputs and enables all support functions.

After start-up, pulling the EN pin low keeps the reference

circuit active, but disables the output transistor and puts

the LT3070 into a lower power “nap” mode. Drive the EN

pin with either a digital logic port or an open-collector NPN

or open-drain NMOS terminated with a pull-up resistor to

VBIAS. The pull-up resistor must be no larger than 35k to

meet the VIH condition of the EN pin. If unused, connect

the EN pin to VBIAS.

Exposed Pad (Pin 29): GND. Tie the Exposed Pad to all

GND pins and directly to the PCB GND. This Exposed Pad

provides enhanced thermal performance with its connec-

tion to the PCB GND. See the Applications Information

section for thermal considerations and calculating junction

temperature.

3070p

9

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