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LT1941

Triple Monolithic Switching Regulator

Linear Technology 

LT1941

PIN FUNCTIONS

VIN (Pins 1, 2, 22, 25): The VIN pins supply current to

the LT1941’s internal circuitry and to the internal power

switches. These pins must be tied to the same source and

locally bypassed.

SW1, SW2, SW3 (Pins 3, 4, 23, 27): The SW pins are

the outputs of the internal power switches. Connect these

pins to the inductors and switching diodes.

BOOST1, BOOST2 (Pins 5, 24): The BOOST pins are used

to provide drive voltages, higher than the input voltage,

to the internal bipolar NPN power switches. Tie through

a diode from VOUT or from VIN.

PGOOD1, PGOOD2, PGOOD3 (Pins 6, 9, 21): The PGOOD

pins are the open-collector outputs of an internal compara-

tor. PGOOD remains low until the FB pin is within 10% of

the final regulation voltage. As well as indicating output

regulation, the PGOOD pins can sequence the switching

regulators. Leave these pins unconnected if unused. The

PGOOD outputs are valid when VIN is greater than 3.5V

and any of the RUN/SS pins are high. They are not valid

when all RUN/SS pins are low.

VC1, VC2, VC3 (Pins 7, 10, 18): The VC pins are the outputs

of the internal error amps. The voltages on these pins

control the peak switch currents. These pins are normally

used to compensate the control loops. Each switching

regulator can be shut down by pulling its respective VC

pin to ground with an NMOS or NPN transistor.

FB1, FB2, FB3 (Pins 8, 11, 20): The LT1941 regulates each

feedback pin to either 0.628V (FB1, FB2) or 1.25V (FB3).

Connect the feedback resistor divider taps to these pins.

RUN/SS1, RUN/SS2, RUN/SS3 (Pins 12, 13, 14): The

RUN/SS pins are used to shut down the individual switching

regulators and the internal bias circuits. They also provide

a soft-start function. To shut down either regulator, pull

the RUN/SS pin to ground with an open drain or collec-

tor. Tie a capacitor from this pin to ground to limit switch

current during start-up. If neither feature is used, leave

these pins unconnected.

BIAS1 (Pin 15): The BIAS1 pin supplies the current to

the LT1941’s internal regulator. Tie this pin to the lowest

available voltage source above 2.35V (Either VIN, VOUT or

any other available supply).

12GOOD (Pin 16): The 12GOOD pin is the open-collector

output of an internal comparator. 12GOOD remains low until

VIN is within 10% of 12V. The pin pulls low when the part

is in shutdown. Leave this pin unconnected if unused.

5GOOD (Pin 17): The 5GOOD pin is the open-collector

output of an internal comparator. 5GOOD remains low until

VIN is within 10% of 5V. The pin pulls low when the part is

in shutdown. Leave this pin unconnected if unused.

NFB (Pin 19): The LT1941 contains an op amp configured

with an output at FB3, noninverting terminal at GND and

an inverting terminal at NFB. Connect the feedback resistor

network virtual ground at this node if regulating negative

voltages. Otherwise, tie this node to FB3.

PGND (Pin 26): Tie directly to local ground plane.

BIAS2 (Pin 28): The BIAS2 pin supplies the current to

the driver of SW3. Tie this pin to the lowest available

voltage source above 2.5V (Either VIN, VOUT or any other

available supply).

Exposed Pad (Pin 29): Ground. The underside Exposed

Pad metal of the package provides both electrical contact

to ground and good thermal contact to the printed circuit

board. The Exposed Pad must be soldered to the circuit

board ground for proper operation.

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