LT1939IDD Ver la hoja de datos (PDF) - Linear Technology
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LT1939IDD Datasheet PDF : 24 Pages
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LT1939
PIN FUNCTIONS
PG (Pin 4): The power good pin is an open-collector
output that sinks current when the FB or LFB falls below
90% of its nominal regulating voltage. For VIN above 2V,
its output state remains true, although during SHDN, VIN
undervoltage lockout, or thermal shutdown, its current
sink capability is reduced.
VC (Pin 5): The VC pin is the output of the error amplifier
and the input to the peak switch current comparator. It is
normally used for frequency compensation, but can also
be used as a current clamp or control loop override. If
the error amplifier drives VC above the maximum switch
current level, a voltage clamp activates. This indicates that
the output is overloaded and current to be pulled from the
SS pin reducing the regulation point.
RT/SYNC (Pin 6): This RT/SYNC pin provides two modes
of setting the constant switch frequency.
Connecting a resistor from the RT/SYNC pin to ground
will set the RT/SYNC pin to a typical value of 1V. The
resultant switching frequency will be set by the resistor
value. The minimum value of 15kΩ and maximum value
of 200kΩ set the switching frequency to 2.5MHz and
250kHz respectively.
Driving the RT/SYNC pin with an external clock signal
will synchronize the switch to the applied frequency.
Synchronization occurs on the rising edge of the clock
signal after the clock signal is detected. Each rising clock
edge initiates an oscillator ramp reset. A gain control loop
servos the oscillator charging current to maintain a con-
stant oscillator amplitude. Hence, the slope compensation
remains unchanged. If the clock signal is removed, the
oscillator reverts to resistor mode and reapplies the 1V
bias to the RT/SYNC pin after the synchronization detection
circuitry times out. The clock source impedance should
be set such that the current out of the RT/SYNC pin in
resistor mode generates a frequency roughly equivalent
to the synchronization frequency. Floating or holding the
RT/SYNC pin above 1.1V will not damage the device, but
will halt oscillation.
PG (Pin 7): The power good bar pin is an open-collector
output that sinks current when the FB or LFB rises above
90% of its nominal regulating voltage.
FB (Pin 8): The FB pin is the negative input to the switcher
error amplifier. The output switches to regulate this pin to
0.8V with respect to the exposed ground pad. Bias current
flows out of the FB pin.
LFB (Pin 9): The LFB pin is the negative input to the linear
error amplifier. The LDRV pin servo’s to regulate this pin to
0.8V with respect to the exposed ground pad. Bias current
flows out of the LFB pin.
LDRV (Pin 10): The LDRV pin is the emitter of an inter-
nal NPN that can be configured as an output of a linear
regulator or as the drive for an external NPN high current
regulator. Current flows out of the LDRV pin when the
LFB pin voltage is below 0.8V. The LDRV pin has a typical
maximum current capability of 13mA.
BST (Pin 11): The BST pin provides a higher than VIN base
drive to the power NPN to ensure a low switch drop. A
comparator to VIN imposes a minimum off time on the SW
pin if the BST pin voltage drops too low. Forcing a SW off
time allows the boost capacitor to recharge.
SW (Pin 12): The SW pin is the emitter of the on-chip
power NPN. At switch off, the inductor will drive this pin
below ground with a high dV/dt. An external catch diode to
ground, close to the SW pin and respective VIN decoupling
capacitor’s ground, must be used to prevent this pin from
excessive negative voltages.
Exposed Pad (Pin 13): GND. The Exposed Pad is the
only ground connection for the device. The Exposed Pad
should be soldered to a large copper area to reduce ther-
mal resistance. The GND pin also serves as small-signal
ground. For ideal operation all small-signal ground paths
should connect to the GND pin at a single point, avoiding
any high current ground returns.
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