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LT1812
(Rev.:RevA)

3mA, 100MHz, 750V/µs Operational Amplifier with Shutdown

Linear Technology 

LT1812

APPLICATIO S I FOR ATIO

Layout and Passive Components

The LT1812 amplifier is more tolerant of less than ideal

layouts than other high speed amplifiers. For maximum

performance (for example, fast settling) use a ground

plane, short lead lengths and RF-quality bypass capacitors

(0.01µF to 0.1µF). For high drive current applications, use

low ESR bypass capacitors (1µF to 10µF tantalum).

The parallel combination of the feedback resistor and gain

setting resistor on the inverting input combine with the

input capacitance to form a pole that can cause peaking or

even oscillations. If feedback resistors greater than 2k are

used, a parallel capacitor of value

CF > RG • CIN/RF

should be used to cancel the input pole and optimize

dynamic performance. For applications where the DC

noise gain is 1 and a large feedback resistor is used, CF

should be greater than or equal to CIN. An example would

be an I-to-V converter.

Input Considerations

Each of the LT1812 amplifier inputs is the base of an NPN

and PNP transistor whose base currents are of opposite

polarity and provide first-order bias current cancellation.

Because of variation in the matching of NPN and PNP beta,

the polarity of the input bias current can be positive or

negative. The offset current does not depend on beta

matching and is well controlled. The use of balanced

source resistance at each input is recommended for

applications where DC accuracy must be maximized. The

inputs can withstand differential input voltages of up to 3V

without damage and need no clamping or source resis-

tance for protection.

The device should not be used as a comparator because

with sustained differential inputs, excessive power dissi-

pation may result.

Capacitive Loading

The LT1812 is stable with a 1000pF capacitive load, which

is outstanding for a 100MHz amplifier. This is accom-

plished by sensing the load induced output pole and

adding compensation at the amplifier gain node. As the

capacitive load increases, both the bandwidth and phase

margin decrease so there will be peaking in the frequency

domain and in the transient response. Coaxial cable can be

driven directly, but for best pulse fidelity, a resistor of

value equal to the characteristic impedance of the cable

(i.e., 75Ω) should be placed in series with the output. The

other end of the cable should be terminated with the same

value resistor to ground.

Slew Rate

The slew rate is proportional to the differential input

voltage. Highest slew rates are therefore seen in the

lowest gain configurations. For example, a 5V output step

in a gain of 10 has a 0.5V input step, whereas in unity gain

there is a 5V input step. The LT1812 is tested for slew rate

in a gain of – 1. Lower slew rates occur in higher gain

configurations.

Shutdown

The LT1812 has a shutdown pin (SHDN, Pin 8) for

conserving power. When this pin is open or biased at

least 2V above the negative supply, the part operates

normally. When pulled down to V –, the supply current

drops to about 50µA. Typically, the turn-off delay is 1µs

and the turn-on delay 0.5µs. The current out of the SHDN

pin is also typically 50µA. In shutdown mode, the ampli-

fier output is not isolated from the inputs, so the LT1812

shutdown feature cannot be used for multiplexing appli-

cations. The 50µA typical shutdown current is exclusive

of any output (load) current. In order to prevent load

current (and maximize the power savings), either the

load needs to be disconnected, or the input signal needs

to be 0V. Even in shutdown mode, the LT1812 can still

drive significant current into a load. For example, in an

AV = 1 configuration, when driven with a 1V DC input, the

LT1812 drives 2mA into a 100Ω load. It takes about

500µs for the load current to reach this value.

Power Dissipation

The LT1812 combines high speed and large output drive

in a small package. It is possible to exceed the maximum

junction temperature under certain conditions. Maximum

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