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LT1641-1 Ver la hoja de datos (PDF) - Linear Technology

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LT1641-1 Datasheet PDF : 12 Pages
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LT1641-1/LT1641-2
APPLICATIO S I FOR ATIO
Figure 9. Short-Circuit Waveforms
VIN
24V
SHORT
PIN
R1
49.9k
1%
R2
3.4k
1%
GND
RS
Q1
0.025IRF530
D2
30V
1N5256B
8
VCC
1
ON
D1
R5
CMPZ
10
5248B
5%
C1
R6, 10nF
1k, 5%
76
SENSE GATE
2
FB
LT1641-1
TIMER
GND
5
4
C2
0.68µF
3
PWRGD
+
VOUT
R3
CL
59k
1%
R7
24k
5%
R4
3.57k
1%
PWRGD
1641-1 F10
Figure 10. Overvoltage Detection
Figure 11. Overvoltage Waveforms
GATE Pin Voltage
A curve of gate drive vs VCC is shown in Figure 13. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
10
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a regular N-FET can be used. In applica-
tions over a 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).
164112fc

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