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LT1161IN

Quad Protected High-Side MOSFET Driver

Linear Technology 

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OPERATIO (Each Channel, Refer to Functional Diagram)

LT1161

The LT1161 gate pin has two states, OFF and ON. In the

OFF state it is held low, while in the ON state it is pumped

to 12V above supply by a self-contained 750kHz charge

pump. The OFF state is activated when either the input pin

is below 1.4V or the timer pin is below 3V. Conversely, for

the ON state to be activated, both the input and timer pins

must be above their thresholds.

When the MOSFET gate voltage is less than 1.4V, the timer

pin is released. The 14µA current source then slowly

charges the timing capacitor back to 3V where the charge

pump again starts to drive the gate pin high. If a fault still

exists, such as a short circuit, the sense comparator

threshold will again be exceeded and the timer cycle will

repeat until the fault is removed (see Figure 2).

If left open, the input pin is held low by a 75k resistor, while

the timer pin is held a diode drop above 3V by a 14µA pull-

up current source. Thus the timer pin automatically re-

verts to the ON state, subject to the input also being high.

The input has approximately 200mV of hysteresis.

The sense pin normally connects to the drain of the power

MOSFET, which returns through a low valued drain sense

resistor to supply. When the gate is ON and the MOSFET

drain current exceeds the level required to generate a

65mV drop across the drain sense resistor, the sense

comparator activates a pull-down NPN which rapidly pulls

the timer pin below 3V. This in turn causes the timer

comparator to override the input pin and activate the gate

pin OFF state, thus protecting the power MOSFET. In order

for the sense comparator to accurately sense MOSFET

drain current, the LT1161 supply pins must be connected

directly to the positive side of the drain sense resistors.

INPUT

OFF

NORMAL

OVERCURRENT

12V

V+

GATE

0V

3V

TIMER

0V

Figure 2. Timing Diagram

NORMAL

1161 F02

APPLICATIONS INFORMATION

Input/Supply Sequencing

There are no input/supply sequencing requirements for

the LT1161. The input may be taken up to 15V with the

supply at 0V. When the supply is turned on with an input

high, the MOSFET turn-on will be inhibited until the timing

capacitor charges to 3V (i.e., for one restart cycle). The

two V+ pins (11, 20) must always be connected to each

other.

Isolating the Inputs

Operation in harsh environments may require isolation to

prevent ground transients from damaging control logic.

The LT1161 easily interfaces to low cost opto-isolators.

The network shown in Figure 3 ensures that the input will

be pulled above 2V, but not exceed the absolute maximum

rating, for supply voltages of 12V to 48V over the entire

temperature range. In order to maintain the OFF state, the

opto must have less than 20µA of dark current (leakage)

hot.

12V TO 48V

100k

LOGIC

2k

1/4 NEC PS2501-4

INPUT

LOGIC

GND

IN

LT1161

51k

POWER

GROUND

GND

GND

1161 F03

Figure 3. Isolating the Inputs

1161fa

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