LRS1386 Ver la hoja de datos (PDF) - Sharp Electronics

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componentes Descripción

Fabricante

LRS1386

Stacked Chip 64M Flash Memory and 8M SRAM

Sharp Electronics 

LRS1386

5

3. Truth Table

3.1 Bus operation(1)

Flash SRAM Notes F-CE F-RST F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ0 to DQ15

Read

3,5

L

Output

Disable

Standby 5

H

L

H

H

(8)

XX

(8)

Write

2,3,4,5

L

(7)

High-Z

DIN

Read

5

LH

(9)

Standby

Output

Disable

5

HHXX

H

H XXLH

High-Z

XXHH

Write

5

XL

(9)

Read 5,6

LH

(9)

Reset Power Output

Down

Disable

5,6

X

HHXX

L XXLH

XXHH

High-Z

Write 5,6

XL

(9)

Standby

5

H

H

Reset Power Standby

Down

5,6

X

XX

L

(8)

XX

(8)

High-Z

Notes:

1. L = VIL, H = VIH, X = H or L. High-Z = High impedance. Refer to the DC Characteristics.

2. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed

when F-VPP = VPPH1/2 and F-VCC = 2.7V to 3.3V.

Block erase, full chip erase, (page buffer) program or OTP program with F-VPP < VPPH1/2 (Min.) produce spurious

results and should not be attempted.

3. Never hold F-OE low and F-WE low at the same timing.

4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation.

5. F-WP set to VIL or VIH.

6. Electricity consumption of Flash Memory is lowest when F-RST = GND ±0.2V.

7. Flash Read Mode

Mode

Read Array

Read Identifier Codes/OTP

Address

X

See 5.2, 5.3

DQ0 to DQ15

DOUT

See 5.2, 5.3

Read Query

Refer to the Appendix

Refer to the Appendix

8. SRAM Standby Mode

S-CE1 S-CE2 S-LB S-UB

H

X

X

X

X

L

X

X

X

X

H

H

9. S-UB, S-LB Control Mode

S-LB S-UB DQ0 to DQ7

L

L

DOUT/DIN

L

H

DOUT/DIN

H

L

High-Z

DQ8 to DQ15

DOUT/DIN

High-Z

DOUT/DIN

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