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LR38637 Ver la hoja de datos (PDF) - Sharp Electronics

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LR38637 Datasheet PDF : 15 Pages
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DSP SERIAL INTERFACE TIMING
LR38637
VIN
0.7DVDD2
VOUT
0.8DVDD2
VOUT
0.9DVDD2
0.3DVDD2
0.2DVDD2
0.1DVDD2
TF
HOST I/F TIMING
SDC In
SDA In
TISS
Fig. 5 I/O Level and Rising Time
Y TIC
R TICL TICH
A TIHS
TISD
TIHD
I N TOAA
TODH
TISP TIHP
SDA Out
M Fig. 6 Host I/F Timing
I (DVDD2 = 3.0 V, DVDD = 2.5 V, TA = –20 to +70˚C)
L PARAMETER
CONDITIONS
SYMBOL
UNIT NOTE
MIN. MAX.
Operating clock frequency
TIC
400 kHz
E High clock period
TICH
0.1
µs
Low clock period
TICL
0.2
µs
Setup time of start condition
TISS
0.1
µs
R Hold time of start condition
TIHS
0.1
µs
P Setup time of input data
TISD
0.1
µs
Hold time of input data
TIHD
0
µs
Output delay
TOAA
0
µs
1
Hold time of output data
TODH
0
µs
1
Setup time of stop condition
TISP
0.1
µs
Hold time of stop condition
TIHP
0.1
µs
Falling period
TF
300 ns
1
NOTE :
1. Output load capacitance CL = 15 pF
13

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