DIGITAL PARALLEL OUTPUT TIMING
LR38637
RCLK
TVSD
VS
HREF
RCLK2
Y7-Y0
UV7-UV0
THREFD
TRCLK2D
TYD
TUVD
INARY
Fig. 4 Digital Parallel Output Timing
M (DVDD2 = 3.0 V, DVDD = 2.5 V, TA = –20 to +70˚C)
I PARAMETER
CONDITIONS
SYMBOL
UNIT NOTE
MIN. MAX.
VS output delay
TVSD –15 +15 ns
1
L HREF output delay
THREFD –15 +15 ns
1
RCLK2 output delay
TRCLK2D –15 +15 ns
1
Y7 to Y0 output delay
TYD
–15 +15 ns
1
E UV7 to UV0 output delay
TUVS –15 +15 ns
1
NOTE :
P R 1. Output load capacitance CL = 15 pF
12