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PCK953BD

50–125 MHz PECL input/CMOS output 3.3 V PLL clock driver

Philips Electronics 

Philips Semiconductors

50–125 MHz PECL input/CMOS output

3.3 V PLL clock driver

Product specification

PCK953

DC CHARACTERISTICS

Tamb = 0 to 70°C; VCC = 3.3 V ±5%

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VIH

Input HIGH voltage LVCMOS inputs

2.0

—

3.6

V

VIL

Input LOW voltage LVCMOS inputs

—

—

0.8

V

Vp-p

Peak-to-peak input voltage PECL_CLK

300

—

1000

mV

VCMR

VOH

VOL

Common mode range

Output HIGH voltage

Output LOW voltage

PECL_CLK

Note 1

IOH = –20 mA;2

IOL = 20 mA;2

VCC–1.5

—

VCC–0.6

mV

2.4

—

—

V

—

—

0.5

V

IIN

Input current

—

—

±75

µA

CIN

Input capacitance

—

—

4

pF

CPD

Power dissipation capacitance

per output

—

25

—

pF

ICC

Maximum quiescent supply current

All VCC pins

—

9

20

mA

ICCPLL Maximum PLL supply current

VCCA pin only

—

9

20

mA

NOTES:

1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within

the VCMR range and the input swing lies within the VPP specification.

2. The PCK953 outputs can drive series or parallel terminated 50 Ω (or 50 Ω to VCC/2) transmission lines on the incident edge (see

Applications info section).

PLL INPUT REFERENCE CHARACTERISTICS

Tamb = 0 to 70°C

SYMBOL

PARAMETER

CONDITION

fref

Reference input frequency

frefDC

Reference input duty cycle

NOTE:

1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.

MIN

MAX

UNIT

20

125

MHz

25

75

%

AC CHARACTERISTICS

Tamb = 0 to 70°C; VCC = 3.3 V ±5%

SYMBOL

PARAMETER

CONDITION

MIN

TYP

tr, tf

tpw

tsk(O)

fVCO

fMAX

Output rise/fall time

Output duty cycle

Output-to–output skews (relative to QFB)

PLL VCO lock range

Maximum output frequency PLL mode

Bypass mode

0.8 V to 2.0 V

VCO_SEL = 1

VCO_SEL = 0

0.30

0.55

45

50

—

—

200

—

20

—

50

tpd(lock)

tpd(by-

pass)

Input to EXT_FB delay (with PLL locked)

Input to Q delay

fref = 50 MHz

PLL bypassed

–75

—

3

5.2

tPLZ-HZ Output disable time

—

tPZL

Output enable time

—

tjitter

Cycle-to-cycle jitter (peak-to-peak)

—

tlock

Maximum PLL lock time

—

NOTE:

1. X will be targeted for 0 ns, but may vary from target by ±150 ps based on characterization of silicon.

—

—

55

0.01

MAX

0.8

55

100

500

100

125

225

125

7

7

6

100

10

UNIT

ns

%

ps

MHz

MHz

MHz

MHz

ps

ns

ns

ns

ps

ms

2001 Feb 08

4

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