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LM3S611 Datasheet PDF : 409 Pages
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LM3S611 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 17
About This Document..................................................................................................................... 19
Audience........................................................................................................................................................... 19
About This Manual............................................................................................................................................ 19
Related Documents .......................................................................................................................................... 19
Documentation Conventions............................................................................................................................. 19
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 22
Product Features ................................................................................................................................. 22
Target Applications .............................................................................................................................. 26
High-Level Block Diagram ................................................................................................................... 27
Functional Overview ............................................................................................................................ 28
ARM Cortex™-M3 ............................................................................................................................... 28
Motor Control Peripherals .................................................................................................................... 28
Analog Peripherals .............................................................................................................................. 29
Serial Communications Peripherals..................................................................................................... 29
System Peripherals.............................................................................................................................. 30
Memory Peripherals............................................................................................................................. 31
Additional Features .............................................................................................................................. 31
Hardware Details ................................................................................................................................. 32
System Block Diagram ........................................................................................................................ 33
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 34
Block Diagram ..................................................................................................................................... 35
Functional Description ......................................................................................................................... 35
Serial Wire and JTAG Debug .............................................................................................................. 35
Embedded Trace Macrocell (ETM) ...................................................................................................... 36
Trace Port Interface Unit (TPIU) .......................................................................................................... 36
ROM Table .......................................................................................................................................... 36
Memory Protection Unit (MPU) ............................................................................................................ 36
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 36
3. Memory Map ........................................................................................................................ 42
4. Interrupts ............................................................................................................................. 44
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
JTAG Interface .................................................................................................................... 47
Block Diagram ..................................................................................................................................... 48
Functional Description ......................................................................................................................... 48
JTAG Interface Pins............................................................................................................................. 49
JTAG TAP Controller ........................................................................................................................... 50
Shift Registers ..................................................................................................................................... 51
Operational Considerations ................................................................................................................. 51
Initialization and Configuration............................................................................................................. 52
Register Descriptions........................................................................................................................... 53
Instruction Register (IR) ....................................................................................................................... 53
Data Registers ..................................................................................................................................... 55
6. System Control.................................................................................................................... 57
6.1 Functional Description ......................................................................................................................... 57
6.1.1 Device Identification............................................................................................................................. 57
April 27, 2007
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