SA8025A Ver la hoja de datos (PDF) - Philips Electronics
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SA8025A Datasheet PDF : 23 Pages
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Philips Semiconductors
1.8GHz low-voltage Fractional-N synthesizer
Product specification
SA8025A
DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Fractional compensation PHP, speed up mode NO TAG, 10 VPHP = VDDA, VRN = VDDA
IPHP_F_S
Fractional compensation output current
PHP vs FRD3
IRF = –62.5µA;FRD = 1 to 713
IRF = –25µA;FRD = 1 to 7
Pump leakage
Charge pump leakage currents, charge pump not active
IPHP_L
Output leakage current PHP; normal
modeNO TAG
VPHP = 0.7 to VDDA – 0.8
IPHI_L
Output leakage current PHI; normal
modeNO TAG
VPHI = 0.7 to VDDA – 0.8
IPHA_L Output leakage current PHA
VPHA = 0.7 to VDDA – 0.8
MIN
–3.35
–1.35
–20
LIMITS
TYP
–2
–1.0
UNITS
MAX
–1.1
–0.5
µA
20
nA
0.1
20
nA
0.1
20
nA
0.1
20
nA
AC ELECTRICAL CHARACTERISTICS
VDD = VDDA = VCCP = 3V; TA = 25°C; unless otherwise specified. Test Circuit, Figure 4. The parameters listed below are tested using
automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate performance limits of the
device. Use of an optimized RF layout will improve many of the listed parameters.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
MIN
TYP
MAX
Main divider guaranteed and tested on an automatic tester. Some performance parameters may be improved by using optimized layout.
fRF_IN Input signal frequency
Pin = -20dBm, Direct coupled input14
0
Pin = -20dBm, 1000pF input coupling
1.8
GHz
1.8
VRF_IN Input sensitivity
Reference divider (VDD = VDDA = 3V or VDD = 3V / VDDA = 5V)
fREF_IN Input signal frequency
VREF_IN Input signal range, AC coupled
fIN = 1800MHz
2.7 < VDD and VDDA < 5.5V
2.7 < VDD and VDDA < 4.5V
2.7 < VDD and VDDA < 5.5V
2.7 < VDD and VDDA < 4.5V
ZREF_IN Reference divider input impedance15
–20
500
300
100
3
0
dBm
25
MHz
30
mVP-P
kΩ
pF
Auxiliary divider
Input signal frequency
0
50
PA = “0”, prescaler enabled
fAUX_IN Input signal frequency
4.5V ≤ VDDA ≤ 5.5V
0
0
150
MHz
30
PA = “1”, prescaler disabled
VAUX_IN Input signal range, AC coupled
ZAUX_IN Auxiliary divider input impedance15
Serial interface15
4.5V ≤ VDDA ≤ 5.5V
0
200
100
3
40
mVP-P
kΩ
pF
fCLOCK
tSU
Clock frequency
Set-up time: DATA to CLOCK,
CLOCK to STROBE
10
MHz
30
ns
tH
Hold time; CLOCK to DATA
Pulse width; CLOCK
tW
Pulse width; STROBE
In-Loop Performance16 VDDA = 5V, VDD = 2.7V
RFMM Main loop residual FM
B, C, D, E words
FVCO = 1780MHz
30
ns
30
ns
30
600
900
Hz
1996 Oct 15
6
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