LH28F800BJB-PTTL90 Ver la hoja de datos (PDF) - Sharp Electronics
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LH28F800BJB-PTTL90 Datasheet PDF : 47 Pages
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LHF80J21
7
2 PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage block
erase, full chip erase, word/byte write and lock-bit
configuration functions. It allows for: fixed power supplies
during block erase, full chip erase, word/byte write and
lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the VCCW voltage. High
voltage on VCCW enables successful block erase, full chip
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents−block
erase, full chip erase, word/byte write, lock-bit
configuration, status and identifier codes−are accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
[A18-A0]
7FFFF
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Top Boot
4KW/8KB Boot Block
4KW/8KB Boot Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
[A18-A-1]
0 FFFFF
FE000
1 FDFFF
FC000
0 FBFFF
FA000
1 F9FFF
F8000
2 F7FFF
F6000
3 F5FFF
F4000
4 F3FFF
F2000
5 F1FFF
F0000
0 EFFFF
E0000
1 DFFFF
D0000
2 CFFFF
C0000
3 BFFFF
B0000
4 AFFFF
A0000
5 9FFFF
90000
6 8FFFF
80000
7 7FFFF
70000
8 6FFFF
60000
9 5FFFF
50000
10 4FFFF
40000
11 3FFFF
30000
12 2FFFF
20000
13 1FFFF
10000
14 0FFFF
00000
Figure 3. Memory Map
Rev. 1.27
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