LH28F800BJB-PTTL10 Ver la hoja de datos (PDF) - Sharp Electronics

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LH28F800BJB-PTTL10

8M (x8/x16) Flash Memory

Sharp Electronics 

LHF80J22

18

Table 6. Status Register Definition

WSMS

BESS

ECBLBS WBWSLBS VCCWS

WBWSS

DPS

R

7

6

5

4

3

2

1

0

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

Check RY/BY# or SR.7 to determine block erase, full chip

erase, word/byte write or lock-bit configuration completion.

SR.6-0 are invalid while SR.7="0".

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS

STATUS (ECBLBS)

1 = Error in Block Erase, Full Chip Erase or Clear Block

Lock-Bits

0 = Successful Block Erase, Full Chip Erase or Clear

Block Lock-Bits

If both SR.5 and SR.4 are "1"s after a block erase, full chip

erase or lock-bit configuration attempt, an improper

command sequence was entered.

SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT

STATUS (WBWSLBS)

1 = Error in Word/Byte Write or Set Block/Permanent

Lock-Bit

0 = Successful Word/Byte Write or Set Block/Permanent

Lock-Bit

SR.3 = VCCW STATUS (VCCWS)

1 = VCCW Low Detect, Operation Abort

0 = VCCW OK

SR.2 = WORD/BYTE WRITE SUSPEND STATUS

(WBWSS)

1 = Word/Byte Write Suspended

0 = Word/Byte Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#

Lock Detected, Operation Abort

0 = Unlock

SR.3 does not provide a continuous indication of VCCW

level. The WSM interrogates and indicates the VCCW level

only after Block Erase, Full Chip Erase, Word/Byte Write or

Lock-Bit Configuration command sequences. SR.3 is not

guaranteed to reports accurate feedback only when

VCCW≠VCCWH1/2.

SR.1 does not provide a continuous indication of permanent

and block lock-bit and WP# values. The WSM interrogates

the permanent lock-bit, block lock-bit and WP# only after

Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit

Configuration command sequences. It informs the system,

depending on the attempted operation, if the block lock-bit is

set, permanent lock-bit is set and/or WP# is VIL. Reading

the block lock and permanent lock configuration codes after

writing the Read Identifier Codes command indicates

permanent and block lock-bit status.

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.0 is reserved for future use and should be masked out

when polling the status register.

Rev. 1.27

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