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LH28F800BJHE-PTTL90

8M (x8/x16) Flash Memory

Sharp Electronics 

LHF80J03

3

1 INTRODUCTION

This datasheet contains the product specifications. Section

1 provides a flash memory overview. Sections 2, 3, 4 and

5 describe the memory organization and functionality.

Section 6 covers electrical specifications.

1.1 Features

Key enhancements of the product are:

•Single low voltage operation

•Low power consumption

•Enhanced Suspend Capabilities

•Boot Block Architecture

Please note following:

•VCCWLK has been lowered to 1.0V to support 2.7V-

3.6V block erase, full chip erase, word/byte write and

lock-bit configuration operations. The VCCW voltage

transitions to GND is recommended for designs that

switch VCCW off during read operation.

1.2 Product Overview

The product is a high-performance 8M-bit Boot Block

Flash memory organized as 512K-word of 16 bits or 1M-

byte of 8 bits. The 512K-word/1M-byte of data is arranged

in two 4K-word/8K-byte boot blocks, six 4K-word/8K-

byte parameter blocks and fifteen 32K-word/64K-byte

main blocks which are individually erasable, lockable and

unlockable in-system. The memory map is shown in

Figure 3.

The dedicated VCCW pin gives complete data protection

when VCCW≤VCCWLK.

A Command User Interface (CUI) serves as the interface

between the system processor and internal operation of the

device. A valid command sequence written to the CUI

initiates device automation. An internal Write State

Machine (WSM) automatically executes the algorithms

and timings necessary for block erase, full chip erase,

word/byte write and lock-bit configuration operations.

A block erase operation erases one of the device’s 32K-

word/64K-byte blocks typically within 1.2s (3V VCC, 3V

VCCW), 4K-word/8K-byte blocks typically within 0.6s (3V

VCC, 3V VCCW) independent of other blocks. Each block

can be independently erased minimum 100,000 times.

Block erase suspend mode allows system software to

suspend block erase to read or write data from any other

block.

Writing memory data is performed in word/byte

increments of the device’s 32K-word blocks typically

within 33µs (3V VCC, 3V VCCW), 64K-byte blocks

typically within 31µs (3V VCC, 3V VCCW), 4K-word

blocks typically within 36µs (3V VCC, 3V VCCW), 8K-

byte blocks typically within 32µs (3V VCC, 3V VCCW).

Word/byte write suspend mode enables the system to read

data or execute code from any other flash memory array

location.

Individual block locking uses a combination of bits, thirty-

nine block lock-bits, a permanent lock-bit and WP# pin, to

lock and unlock blocks. Block lock-bits gate block erase,

full chip erase and word/byte write operations, while the

permanent lock-bit gates block lock-bit modification and

locked block alternation. Lock-bit configuration

operations (Set Block Lock-Bit, Set Permanent Lock-Bit

and Clear Block Lock-Bits commands) set and cleared

lock-bits.

The status register indicates when the WSM’s block erase,

full chip erase, word/byte write or lock-bit configuration

operation is finished.

The RY/BY# output gives an additional indicator of WSM

activity by providing both a hardware signal of status

(versus software polling) and status masking (interrupt

masking for background block erase, for example). Status

polling using RY/BY# minimizes both CPU overhead and

system power consumption. When low, RY/BY# indicates

that the WSM is performing a block erase, full chip erase,

word/byte write or lock-bit configuration. RY/BY#-high Z

indicates that the WSM is ready for a new command,

block erase is suspended (and word/byte write is

inactive), word/byte write is suspended, or the device is in

reset mode.

Rev. 1.27

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