LH521028 Ver la hoja de datos (PDF) - Sharp Electronics

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LH521028

CMOS 64K × 18 Static RAM

Sharp Electronics 

LH521028

CMOS 64K × 18 Static RAM

TIMING DIAGRAMS – READ CYCLE

Read Cycle No. 1 (Unlatched Address Controlled

Read)

Chip is in Read Mode: ALE is HIGH (transparent

mode), E and G are LOW. Read cycle timing is referenced

from when all addresses are stable until the first address

transition. Following a W-controlled Write cycle, tWA and

tAA must both be satisfied to ensure valid data. Cross-

hatched portion of Data Out implies that data lines are in

the Low-Z state but the data is not guaranteed to be valid

until tAA.

Read Cycle No. 2 (Unlatched Chip Enable

Controlled Read)

Chip is in Read Mode: ALE is HIGH (transparent

mode). Read cycle timing is referenced from when E, S,

and G are stable until the first address transition. Cross-

hatched portion of Data Out implies that data lines are in

the Low-Z state but the data is not guaranteed to be valid.

ADDRESS

W

DQ

tRC

VALID ADDRESS

tWA

tAA

PREVIOUS DATA

tOH

VALID DATA

Figure 4. Read Cycle No. 1

521028-2

ADDRESS

W

E

SL, SH

G

DQ

tRCS

VALID ADDRESS

tEA

tSA

tGA

tGLZ

tSLZ

tELZ

tRCH

tEHZ

tSHZ

tGHZ

VALID DATA

Figure 5. Read Cycle No. 2

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