LH5164ASH Ver la hoja de datos (PDF) - Sharp Electronics

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LH5164ASH

CMOS 64K (8K × 8) Static RAM

Sharp Electronics 

CMOS 64K (8K × 8) Static RAM

LH5164ASH

DATA RETENTION CHARACTERISTICS (TA = -40 to +85°C)

PARAMETER

Data retention supply voltage

Data retention supply current

SYMBOL

VCCDR

ICCDR

CONDITIONS

CE2 ≤ 0.2 V or

CE1 ≥ VCCDR – 0.2 V

VCCDR = 3 V,

CE2 ≤ 0.2 V or

CE1 ≥ VCCDR – 0.2 V

TA = 25°C

TA = 40°C

Chip disable to data retention

tCDR

Recovery time

tR

NOTES:

1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR - 0.2 V.

2. tRC = Read cycle time

MIN.

2.0

0

tRC

MAX.

5.5

0.2

0.4

0.6

UNIT NOTE

V

1

µA

µA

1

µA

ns

ns

2

CE1 CONTROL (NOTE)

DATA RETENTION MODE

VCC

tCDR

tR

2.5 V

VCC - 0.5 V

VCCDR

CE1

0V

CE1 ≥ VCCDR - 0.2 V

CE2 CONTROL

VCC

CE2

2.5 V

DATA RETENTION MODE

tCDR

tR

VCCDR

0.2 V

0V

CE2 0.2 V

NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V

during the data retention.

Figure 4. Low Voltage Data Retention

5164ASH-6

5

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