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3293-04 Ver la hoja de datos (PDF) - Peregrine Semiconductor

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3293-04 Datasheet PDF : 18 Pages
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Product Description
The PE3293 is a dual fractional-N phase-lock loop (PLL)
IC designed for frequency synthesis and fabricated on
Peregrine’s patented UTSi® CMOS process. Each PLL
includes a prescaler, phase detector, charge pump and
on-board fractional spur compensation.
The patented spur compensation circuitry designed into
the device ensures superior spur performance over the
full temperature and VCO tuning range.
The PE3293 provides fractional-N division with power-of-
two denominator values up to 32. This allows
comparison frequencies up to 32 times the channel
spacing, providing a lower phase noise floor than integer
PLLs. The 32/33 RF prescaler (PLL1) operates up to 1.8
GHz and the 16/17 IF prescaler (PLL2) operates up to
550 MHz.
Applications
Triple mode,dual-band PCS / Cellular handset
PCS/CDMA/Cellular handsets
PCS/CDMA/Cellular base stations
Figure 1. Block Diagram
PRODUCT SPECIFICATION
PE3293
1.8 GHz / 550 MHz Dual
Fractional-N Ultra-Low
Spurious PLL for Frequency
Synthesis
Features
Industry leading fractional spur
compensation: no adjusting
required, stable over temp.
Ultra-Low Power consumption:
4.0 mA typical, both loops
operating
Modulo-32 fractional-N main
counters
Supply voltage range 2.7 to 3.3
VDC
fin1
32/33
Prescaler
19-bit Fractional-N
Main Divider
Fractional Spur
Compensation
fr
Clock
Data
LE
Ref.
Amp.
9-bit Reference
Divider
21-bit Serial Control
Interface
Phase
Charge
CP1
Detector
Pump
Multiplexer
foLD
9-bit Reference
Divider
Phase
Charge
CP2
Detector
Pump
fin2
16/17
Prescaler
18-bit Fractional-N
Main Divider
Fractional Spur
Compensation
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 18

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