LH28F040SUT-Z4 Ver la hoja de datos (PDF) - Sharp Electronics

Número de pieza

componentes Descripción

Fabricante

LH28F040SUT-Z4

4M (512K × 8) Flash Memory

Sharp Electronics 

LH28F040SUTD-Z4

4M (512K × 8) Flash Memory

DESCRIPTION

The LH28F040SUTD-Z4 is a high performance 4M

(4,194,304 bit) block erasable non-volatile random

access memory organized as 256K × 8 × 2 banks. The

LH28F040SUTD-Z4 includes thirty-two 16K (16,384)

blocks. A chip memory map is shown in Figure 3.

The two banks, the one selected by BE0» (bank0) and

the other selected by BE »1 (bank1) can be controlled

independently. For example, while erase the data in

bank0, the data in bank1 can be read out.

The implementation of a new architecture, with many

enhanced features, will improve the device operating

characteristics and results in greater product reliability

and ease of use.

Among the significant enhancements of the

LH28F040SUTD-Z4:

• 3 V Read, 5 V Write/Erase Operation

(5 V VPP, 3 V VCC)

• Low Power Capability (2.7 V VCC Read)

• Improved Write/Erase Performance

(Two-Byte Serial Write, Bank Erase)

• Dedicated Block Write/Erase Protection

• Command-Controlled Memory Protection

Set/Reset Capability

The LH28F040SUTD-Z4 will be available in a 40-pin,

1.2 mm thick × 10 mm × 20 mm TSOP (Type I) pack-

age.This form factor and pinout allow for very high board

layout densities.

A Command User Interface (CUI) serves as the sys-

tem interface between the microprocessor or micro-

controller and the internal memory operation.

Internal Algorithm Automation allows Byte Writes and

Block Erase operations to be executed using a Two-

Write command sequence to the CUI in the same way

as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher

write performance and provide additional capabilities.

These new commands and features include:

• Software Locking of Memory Blocks

• Memory Protection Set/Reset Capability

• Two-Byte Serial Writes in 8-bit Systems

• Bank Erase All Unlocked Blocks

Writing of memory data is performed typically within

20 µs. A Block Erase operation erases one of the 32

blocks in typically 1.5 seconds, independent of the other

blocks.

LH28F040SUTD-Z4 allows to erase all unlocked

blocks for each bank selected by BE »0 or BE »1. It is de-

sirable in case of which you have to implement Erase

operation maximum 32 times.

LH28F040SUTD-Z4 enables Two-Byte serial Write

which is operated by three times command input. This

feature can improve system write performance by up to

typically 17 µs per byte.

All operations are started by a sequence of Write

commands to the device. Status Register (described in

detail later) provide information on the progress of the

requested operation.

Same as the LH28F008SA, LH28F040SUTD-Z4

requires an operation to complete before the next op-

eration can be requested, also it allows to suspend block

erase to read data from any other block, and allow to

resume erase operation.

The LH28F040SUTD-Z4 provides user-selectable

block locking to protect code or data such as Device

Drivers, PCMCIA card information, ROM-Executable OS

or Application Code. Each block has an associated non-

volatile lock-bit which determines the lock status of the

block. In addition, the LH28F040SUTD-Z4 has a soft-

ware controlled master Write Protect circuit which pre-

vents any modifications to memory blocks whose lock-

bits are set.

When the device power-up, Write Protect Set/

Confirm command must be written both in bank0 and

bank1. Otherwise, all lock bits in the device remain

being locked, can’t perform theWrite to each block and

single Block Erase.Write Protect Set/Confirm command

must be written to reflect the actual lock status. How-

ever, when the device power-on, Erase All Unlocked

Blocks can be used. If used, Erase is performed with

reflecting actual lock status, and after that Write and

Block Erase can be used.

The LH28F040SUTD-Z4 contains Status Register to

accomplish various functions:

• A Compatible Status Register (CSR) which is

100% compatible with the LH28F008SA Flash

memory’s Status Register. This register, when used

alone, provides a straightforward upgrade capabil-

ity to the LH28F040SUTD-Z4 from a LH28F008SA

based design.

The LH28F040SUTD-Z4 is specified for a maximum

access time of 150 ns (tACC) at 3.3 V operation (3.0 to

3.6 V) over the commercial temperature range (-20 to

+70°C). A corresponding maximum access time of

190 ns (tACC) at 2.7 V (-20 to +70°C) is achieved for

reduced power consumption applications.

4

Share Link: