LB11872H(2002) Ver la hoja de datos (PDF) - SANYO -> Panasonic
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LB11872H Datasheet PDF : 13 Pages
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LB11872H
6. Rotor Constraint Protection Circuit
This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is
constrained physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the
IN1 signal) does not switch within a fixed time, output drive will be turned off. The time constant is determined by
the capacitor connected to the CSD pin.
<time constant (in seconds)> .=. 30.5 × 1.57 × CCSD (µF)
If a 0.02 µF capacitor is used, the protection time will be about 1.05 seconds.
To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off
and reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection
circuit may not operate normally.
7. Phase Lock Signal
(1) Phase lock range
Since this IC does not include a counter or similar functionality in the speed control system, the speed error range
in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the
changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the
motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in
states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at
startup and when unlocked due to switching clock frequencies.
(2) Masking function for the phase lock state signal
A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pull-
in. However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CSD pin and ground.
<masking time (seconds)> .=. 6.5 × 1.57 × CCSD (µF)
When a 0.022 µF capacitor is used, the masking time will be about 225 ms. In cases where complete masking is
required, a masking time with fully adequate margin must be used.
8. Initial Reset
To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero
until it reaches 0.63 V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good
approximation using the following formula.
<reset time (seconds)> .=. 0.13 × CCSD (µF)
A reset time of over 100 µs is required.
9. Current Limiter Circuit
The current limit value is determined by the resistor Rf inserted between the RF pin and ground.
ILIM = VL/Rf VL = 0.59 V (typical) (during acceleration) and 0.37 V (typical) (during deceleration)
10. Power Supply Stabilization
An adequately large capacitor must be inserted between the VCC pin and ground for power supply stabilization. If
diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected
with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must
be used.
If high-frequency noise is a problem, a ceramic capacitor of about 0.1 µF must also be inserted in parallel.
No. 7257 -11/13
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