L6562AT Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
componentes Descripción
Fabricante
L6562AT Datasheet PDF : 25 Pages
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Pin settings
2
Pin settings
2.1
Pin connection
Figure 2. Pin connection (top view)
INV 1
COMP 2
MULT 3
CS 4
8 Vcc
7 GD
6 GND
5 ZCD
L6562AT
2.2
Pin description
Table 2. Pin description
Pin N° Name
Description
Inverting input of the error amplifier. The information on the output voltage of
1
INV
the PFC pre-regulator is fed into this pin through a resistor divider. The pin
doubles as an ON/OFF control input.
Output of the error amplifier. A compensation network is placed between this
2
COMP pin and INV to achieve stability of the voltage control loop and ensure high
power factor and low THD.
Main input to the multiplier. This pin is connected to the rectified mains
3
MULT voltage via a resistor divider and provides the sinusoidal reference to the
current loop.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared
4
CS
with an internal sinusoidal-shaped reference, generated by the multiplier, to
determine MOSFET’s turn-off. The pin is equipped with 200 ns leading-edge
blanking for improved noise immunity.
5
ZCD
Boost inductor’s demagnetization sensing input for transition-mode
operation. A negative-going edge triggers MOSFET’s turn-on.
6
GND
Ground. Current return for both the signal part of the IC and the gate driver.
Gate driver output. The totem pole output stage is able to drive power
7
GD
MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA
sink. The high-level voltage of this pin is clamped at about 12 V to avoid
excessive gate voltages in case the pin is supplied with a high Vcc.
Supply voltage of both the signal part of the IC and the gate driver. The
8
Vcc
supply voltage upper limit is extended to 22 V min. to provide more
headroom for supply voltage changes.
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