L4975 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

L4975

5A SWITCHING REGULATOR

STMicroelectronics 

L4975A

PIN FUNCTIONS

No

Name

1

OSCILLATOR

2

OSCILLATOR

3

RESET INPUT

4

RESET OUT

5

RESET DELAY

6

BOOTSTRAP

7

OUTPUT

8

GROUND

9

SUPPLY VOLTAGE

10 FREQUENCY

COMPENSATION

11 FEEDBACK INPUT

12 SOFT START

13 SYNC INPUT

14

Vref

15

Vstart

Function

Rosc. External resistor connected to ground determines the constant charging

current of Cosc.

Cosc. External capacitor connected to ground determines (with Rosc) the

switching frequency.

Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a

divider to the input for power fail function. It must be connected to the pin 14 an

external 30KΩ resistor when power fail signal not required.

Open Collector Reset/power Fail Signal Output. This output is high when the

supply and the output voltages are safe.

A Cd capacitor connected between this terminal and ground determines the

reset signal delay time.

A Cboot capacitor connected between this terminal and the output allows to

drive properly the internal D-MOS transistor.

Regulator Output.

Common Ground Terminal

Unregulated Input Voltage.

A series RC network connected between this terminal and ground determines

the regulation loop gain characteristics.

The Feedback Terminal of the Regulation Loop. The output is connected

directly to this terminal for 5.1V operation; It is connected via a divider for higher

voltages.

Soft Start Time Constant. A capacitor is connected between thi sterminal and

ground to define the soft start time constant.

Multiple L4975A are synchronized by connecting pin 13 inputs together or via

an external syncr. pulse.

5.1V Vref Device Reference Voltage.

Internal Start-up Circuit to Drive the Power Stage.

CIRCUIT OPERATION (refer to the block dia-

gram)

The L4975A is a 5A monolithic stepdown switching

regulator working in continuous mode realized in

the new BCD Technology. This technology allows

the integration of isolated vertical DMOS power

transistors plus mixed CMOS/Bipolar transistors.

The device can deliver 5A at an output voltage

adjustable from 5.1V to 40V, and contains diag-

nostic and control functions that make it particu-

larly suitable for microprocessor based systems.

BLOCK DIAGRAM

The block diagram shows the DMOS power tran-

sistor and the PWM control loop. Integrated func-

tions include a reference voltage trimmed to 5.1V

± 2%, soft start, undervoltage lockout, oscillator

with feedforward control, pulse by pulse current

limit, thermal shutdown and finally the reset and

power fail circuit. The reset and power fail circuit

provides an output signal for a microprocessor in-

dicating the status of the system.

Device turn on is around 11V with a typical 1V

hysteresis, this threshold provides a correct volt-

age for the driving stage of the DMOS gate and

the hysteresis prevents instabilities.

An external bootstrap capacitor charged to 12V

by an internal voltage reference is needed to pro-

vide correct gate drive to the power DMOS. The

driving circuit is able to source and sink peak cur-

rents of around 0.5A to the gate of the DMOS

transistor. A typical switching time of the current

in the DMOS transistor is 50ns. Due to the fast

commutation switching frequencies up to 500kHz

are possible.

The PWM control loop consists of a sawtooth os-

cillator, error amplifier, comparator, latch and the

output stage. An error signal is produced by com-

paring the output voltage with the precise 5.1V ±

2% on chip reference. This error signal is then

compared with the sawtooth oscillator, in order to

generate a fixed frequency pulse width modulated

drive for the output stage. A PWM latch is in-

cluded to eliminate multiple pulsing within a pe-

riod even in noisy environments. The gain and

3/21

Share Link: