Shenzhen KYL Communication Equipment Co., Ltd
Timing diagram:
b. The delay time of transceivers between the first bit sent by TxD to the
first bit received by RxD.
Due to a data processing will be made on user’s data by KYL-500S
transceiver using FEC (Forward Error Correction) or other correction
algorithm, when RxD of a KYL-500S transceiver ‘A’ receives the data,
then transmits it, the other one transceiver ‘B’ will have a delay (ts) to
receive and transmit by TxD. Different RF data rate causes different delay
time. Please see the specific delay time
below:
RF Date Rate
(bps)
1200
2400
4800
Delay
Ts(mS)
90
48
30
RF Date Rate
(bps)
9600
19200
Delay
Ts(mS)
16
10
Timing diagram:
c. Error dealing procedure:
To enhance the reliability and stability of user’s systems, a verify bit or a Cyclic
Redundancy Check (CRC) mode is highly recommended to resent the wrong
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