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SAA2003H

Stereo filter and codec

Philips Electronics 

Philips Semiconductors

Stereo filter and codec

Preliminary specification

SAA2003

handbook, full pagewidth

STANDBY

MODE 1

t1

RESET

CLK24/CLK22

ACTIVE

I/O's

ACTIVE

MODE 2

MODE 3

t2

t3

MODE 4

STATIC

ACTIVE

ACTIVE

MBD622

Fig.7 Reset and sleep timing.

Table 1 Reset and sleep timing modes (see Fig.7).

MODE

MODE1

MODE2

MODE3

MODE4

DESCRIPTION

standby stage 1; clocks still running

standby mode; clocks stopped

clocks running; reset active

normal operational mode

TIMING

t1

t2

t3

−

MIN.

400

0

1

−

MAX.

−

−

−

−

UNIT

ns

ns

ms

Sleep mode

A HIGH input applied to the SLEEP pin halts all internally generated clock signals. If the transparent mode of the serial

audio interface is set before entering sleep, the data at the X256 external clock input is sent to the FS256 output and the

data at SD1 input is sent to the SD2 output. If transparent mode is not set, these two outputs are high impedance during

sleep mode.

The IECOP pin is set to high impedance during sleep mode, unless the transparent mode is selected and WS-SEL is set.

May 1994

9

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