SAA5284 Ver la hoja de datos (PDF) - Philips Electronics

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componentes Descripción

Fabricante

SAA5284

Multimedia video data acquisition circuit

Philips Electronics 

Philips Semiconductors

Multimedia video data acquisition circuit

Objective specification

SAA5284

8.9 Host interface

The SAA5284 has a multi-standard 8-bit I/O interface.

To reduce the amount of host I/O space used, the parallel

interface has only 3 address inputs (A0, A1 and A2).

An extended addressing (pointer) scheme and the data

FIFO are used to allow access to the full set of SAA5284

registers and the full span of the packet buffer.

As well as the 8 data I/O lines and 3 address lines, there

are the following control signals: RD (read LOW), WR

(write LOW), CS0 (chip select LOW), CS1(second chip

select LOW), INT (interrupt request), DMARQ (DMA

request), DMACK (DMA acknowledge) and RDY (ready).

In order to maintain compatibility with Motorola and Intel

type buses, two control signals SEL0 and SEL1 are

provided to configure the host interface. These signals

allow configuration of the host interface to work with the

Motorola or Intel style interfaces.

The host interface has a digital video mode. Digital video

mode may be used to allow the SAA5284 to pass decoded

VBI data into a system using the digital video bus.

8.10 Interrupt support

The host interface provides comprehensive support for

interrupt generation. The interrupt may be programmed to

occur when a particular number of packets of VBI data are

available in the cache RAM. The interrupts can be further

controlled to occur on a specific line in the TV frame.

The interrupts can also be self masking if required.

8.11 DMA support

Burst and demand mode DMA are supported. In burst

mode, the number of packets to transfer can be defined.

An interrupt can be generated when DMA is finished. This

can be self masking.

8.12 I2C-bus interface

The I2C-bus interface functions as a slave receiver or

transmitter at up to 400 kHz. The I2C-bus address is

selectable as 20H or 22H. All functionality is available

using the I2C-bus although with a slower data transfer

speed. It is possible to use the I2C-bus in all modes.

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

VDD

VI(max)

VO(max)

∆VDDD−DDA−DDX

IIOK

IO(max)

Tstg

Tamb

supply voltage (all supplies)

input voltage (any input)

output voltage (any output)

supply voltage difference between VDDD, VDDA and VDDX

DC input or output diode current

output current (any output)

storage temperature

operating ambient temperature

MIN.

−0.3

−0.3

−0.3

−

−

−

−55

−20

MAX.

+6.5

VDD + 0.5

VDD + 0.5

0.25

20

10

+125

+70

UNIT

V

V

V

V

mA

mA

°C

°C

10 QUALITY & RELIABILITY

In accordance with “SNW-FQ-611-E”.

1998 Feb 05

8

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