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SAA5284

Multimedia video data acquisition circuit

Philips Electronics 

Philips Semiconductors

Multimedia video data acquisition circuit

Objective specification

SAA5284

5 MAIN FUNCTIONAL BLOCKS

1. Input clamp and sync separator

2. Analog-to-digital converter

3. Multi-standard data slicer and clock regenerator

4. Packet filtering; (8 and 4) Hamming correction

5. On-chip data cache

6. Line selectable data type

6 BLOCK DIAGRAM

7. 12, 13.5, 15 and 16 MHz clock or oscillator options

8. FIFO access to data

9. Interrupt and DMA support

10. Multi-standard parallel interface

11. I2C-bus interface

12. Power-on reset.

Figure 1 shows a block diagram of the SAA5284.

handbook, full pagewidth

VDDA VSSA VDDX VDDD VSSD3

RESET VPOIN0 HREF

LLC

VPOIN1 LLC2

RD(1) DMACK(1)

WR(1) DMARQ

16 17 6

41 40

1

38 39 2 43 42

33 34 36 37

CVBS0 15

14

CVBS1

SAA5284

ANALOG

SWITCH

PACKET BUFFER AND

FRONT END CONTROL

REGISTERS

MULTI-STANDARD

HOST INTERFACE

35

44

31

32

10

11

5

30 to 28 3

20 to 27 8

CS0

CS1

INT

RDY(1)

SEL0

SEL1

DENB

A2 to A0(1)

D7 to D0(1)

IREF 13

BLACK 12

ANALOG

VIDEO TO

DATA BYTE

CONVERTER

(DATA

DEMODULATOR)

PACKET

FILTERING (e.g.

WST packets

30/31)

FIFO

I2C-BUS

INTERFACE

400 kHz

SLAVE

3

SDA

4

SCL

OSCILLATOR

AND TIMING

7

8

9

OSCOUT

OSCGND

OSCIN

PACKET BUFFER RAM

2 kbyte

(45 packets)

18

19

VSSD1

VSSD2

MGG740

data path

control

(1) Multi-functional pins, see Chapter 7.

Fig.1 Block diagram.

1998 Feb 05

4

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