74F256 Ver la hoja de datos (PDF) - Philips Electronics
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74F256 Datasheet PDF : 12 Pages
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Philips Semiconductors
Dual addressable latch
Product specification
74F256
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
tPLH
Propagation delay
tPHL
Dn to Qn
tPLH
Propagation delay
tPHL
E to Qn
tPLH
Propagation delay
tPHL
An to Qn
tPHL
Propagation delay
MR to Qn
TEST
CONDITION
Waveform 2
Waveform 1
Waveform 3
Waveform 4
LIMITS
Tamb = +25°C
VCC = +5V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5V ± 10%
CL = 50pF, RL = 500Ω
MIN TYP MAX
MIN
MAX
4.0
7.0
9.5
4.0
10.0
3.0
5.0
7.0
2.5
7.5
4.5 8.0 10.5
4.5
12.0
3.0
5.0
7.0
3.0
7.5
5.0 10.0 14.0
5.0
14.5
4.5
8.5
9.5
4.0
10.0
5.0
7.0
9.0
4.5
10.0
UNIT
ns
ns
ns
ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL= 50pF, RL = 500Ω
MIN TYP MAX
MIN
MAX
UNIT
ts(H)
ts(L)
Setup time, High or Low
Dn to E
Waveform 5
3.0
6.5
3.0
ns
7.0
th(H)
th(L)
Hold time, High or Low
Dn to E
Waveform 5
0
0
0
ns
0
ts(H)
ts(L)
Setup time, High or Low
An to E1
Waveform 6
2.0
2.0
2.0
ns
2.0
th(H)
th(L)
Hold time, High or Low
An to E2
Waveform 6
0
0
0
ns
0
tw(L) E Pulse width, Low
Waveform 1
7.5
8.0
ns
tw(L) MR Pulse width, Low
Waveform 4
3.0
3.0
ns
NOTES:
1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
1988 Nov 29
6
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